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Cutting-Edge Readout Concept for Pixel Detectors

Explore the novel concept for future pixel detectors focusing on current-mode signal processing, developed by Marcel Trimpl at Bonn University and MPI Munich. The concept features fast, low-noise readout utilizing DEPFET technology with excellent energy resolution and low power consumption. The proposed architecture enables efficient row-wise readout and hit identification, enhancing detector performance. Discover the innovative design principles and test setups aiding in achieving high speed, accuracy, and reduced charge injection for optimal detector operation.

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Cutting-Edge Readout Concept for Pixel Detectors

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  1. Vertex 2002 Kailua-Kona, November 2002 Readout Concept for Future Pixel Detectors based on Current Mode Signal Processing Marcel Trimpl Bonn University Bonn University / MPI Munich (HLL) L.Andricek, G.Lutz, P.Lechner, R.H.Richter, L.Strüder P.Fischer, I.Peric, M.Trimpl, J.Ulrici, N.Wermes Marcel Trimpl, Bonn University

  2. single-pixel spectra: Matrix-picture with 55Fe: [J.Ulrici, Bonn] ~ 3.2 mm 55Fe-spectra @ 300K spatial resolution: ~ 9µm (with 50x50 µm2 pixel) ENC = 4.8 +/- 0.1 e- DEPFET-Performance • excellent energy resolution • (low noise needed for thinned detector) • thinnable (50µm proposed for TESLA) • small pixelsize possible (25x25µm2) • good spatial resolution (charge sharing) • low power consumption • (< 1W for whole TESLA vtx-sensor) • (row-wise operation) Þfast and low noise readout needed !! Marcel Trimpl, Bonn University

  3. Proposed concept for TESLA matrix is read out row-wise first thinned samples: • thin detector-area • down to 50µm • frame for mechanical • stability carries readout- • and steering-chips [L.Andricek, MPI Munich] Marcel Trimpl, Bonn University

  4. Advantages of readout: But: complete reset (clear) needed • pedestals need not to be stored • 1/f noise is reduced (CDS) • continue with next row ... Matrixoperation Matrix-scheme: Readout-scheme: • Select one row via external Gates and measure Pedestal + Signal current • Reset one row and measure pedestal currents • Collected charge in internal gate ~ (Difference of both currents) Marcel Trimpl, Bonn University

  5. Readout Architecture V1.0 DEPFET provides current + fast readout needed Þ current readout • Regulated Cascode keeps drain potential constant • (Signal+Pedestal) are stored in fast current memory cell (20ns, inverting) • Pedestal-Current after Reset is subtracted automatically • Hit-Identification with fast current comparator • Hit-Information + analog value are stored in mixed-signal FIFO • FIFO is emptied row by row Fast digital scanner identifies hits in a row (up to 2 hits per cycle) and multiplexes the corresponding analog currents to the outputs (no external trigger) Marcel Trimpl, Bonn University

  6. ... and ... it is easy to add new features • larger buffer to store several rows at front end • possible (if reset is not fast enough) • analog signals: row-wise common-mode-rejection • reduces common noise pickup remarkably • digital signals: neighbour logic • (mark neighbour pixel of hit for readout • even if they are below threshold) • more hit scanners can easily be added • (if occupancy is higher than at TESLA) • on chip (algorithmic) ADC at the end • (only needs to digitize hits – saves power) Marcel Trimpl, Bonn University

  7. IDEPFET I = IDEPFET + IBias I = IDEPFET + IBias Basic Storage Principle Storage phase: input- and sample-switch are closed. (storage capacitance is „parasitic“ gate-capacitance of nmos) Sampling phase: sample and input switch are opened ( voltage at capacitance „unchanged“ → current unchanged ) Transfer phase: Output switch is closed. IDEPFET is flowing out. (done immediately after sampling) Marcel Trimpl, Bonn University

  8. Prototype-Chip 1.5mm 4 mm • TSMC 0.25 µm process with radiation-tolerant layout • contains all basic parts of proposed design • (various memory-cells, fast hit-finder, current comparator structures) Marcel Trimpl, Bonn University

  9. high speed and high accurancy ... 1. Bandwidth (speed – intrinsically high because of small capacitance) 2. Output conductance (negligible with cascode techniques) 3. charge injection (offset and signal depending) 4. Noise (sampling noise dominant) 5. Radiation tolerant design limits transistor parameters (geometry has to be angular) Marcel Trimpl, Bonn University

  10. reduce charge injection Use of 2 stages: coarse and fine sampling Error of coarse stage is resampled by fine stage ÞSignal depending charge injection reduced If two successive sample-stages are used (like in readout-architecture) the offset is eliminated as well: Iout1 = - Iin + ddI Iout2 = - Iin + ddI = Iin + ddI – ddI = Iin Marcel Trimpl, Bonn University

  11. Testsetup for Memory Cells input U2I I2U Memory Cell steering I2U U2I ADC Marcel Trimpl, Bonn University

  12. 0.1% accurancy reached @ 25MHz !! measured linearity 2 memory cells with regulated cascode input (like in readout architecture) dynamic range depends on bias-current of memory cell (range vs. power) (10µA for DEPFET-readout needed) Marcel Trimpl, Bonn University

  13. Realistic model: careful design needed to avoid oscillation ... Bandwith (speed) Simple model: High speed : small Cgate, large gm Still : small Cgate large gm for high speed Marcel Trimpl, Bonn University

  14. current sample-stage: Low noise: Large C, small gm (contrary to high speed requirement) Noise from current sampling voltage sample-stage: (independent of RSwitch) Marcel Trimpl, Bonn University

  15. sampling noise Noise [ nA] • gm and CGate are not independent: • linked via geometry • speed requirement gives ratio • (line indicating 50MHz) present design (23 ... 29nA) ~ 30 electrons sampling noise ( assuming gQ = 1nA /e- ) more than other noise contributions (e.g. pmos current source) Marcel Trimpl, Bonn University

  16. measured noise • low noise expected • (< 30 electrons) • difficult to measure • with simple testsetup → cascade ofsampling stages on chip corresponds to calculation !! Marcel Trimpl, Bonn University

  17. Summary of performance digital part: fast hit-finder and current-comparator-block work with desired speed (50MHz) analog part (memory cell): speed: 25MHz accurancy : 0.1 % noise : < 30 electrons very encouraging result  Marcel Trimpl, Bonn University

  18. next step .... TESLA prototype-system: • full 128 channel readout-chip • working with DEPFET-Matrix • at 50MHz • Internal ADC optional • Timing at TESLA : • » 1ms Trainbunch • » 200ms Trainpause • Hits are stored in RAM • during train and read out in pause Marcel Trimpl, Bonn University

  19. Summary / Outlook • Concept with fast readout for HEP-Experiment • (e.g. TESLA) with current mode signal processing presented • Architecture of current mode operating prototype-chip • has a lot of advantages (low power, high linearity, high speed, • wide dynamic range) and is versatile • First prototype shows encouraging results with • nearly TESLA requirements: • Speed has to be improved by better choice • of cell parameters : 50MHz possible • TESLA Prototype-System working with DEPFET-Matrix • expected within 2003 Marcel Trimpl, Bonn University

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