RAMP: Architecture, Language & Compiler

1. RAMP: Architecture, Language & Compiler http://ramp.eecs.berkeley.edu Greg Gibeling, Andrew Schultz, Krste Asanovic Contact: gdgib@berkeley.edu RAMP Retreat, BWRC, 20 January 2006 RAMP Architecture, Language & Compiler

2. CPU CPU CPU CPU Interconnect Network DRAM 2VP70 FPGA 2VP70 FPGA 2VP70 FPGA 2VP70 FPGA 2VP70 FPGA RDL Compiled to FPGA Emulation RDL Compiled to Software Simulation BEE2 Host Platform Workstation Host Platform RAMP Design Framework Overview • Target System: the machine being emulated • Describe structure in RAMP Description Language (RDL) • Describe behavior of each leaf unit in favorite language (Verilog, VHDL, Bluespec, C/C++, Java) • Host Platforms: systems that run the emulation or simulation • Can have part of target mapped to FPGA emulation and part mapped to software simulation RAMP Architecture, Language & Compiler

3. RAMP Target Model (1) Units communicating over channels • Units • Large pieces of functionality, >10,000 Gates • e.g., Processor + L1$ • Leaf units implemented in a “host” language • Channels • Unidirectional • Point-to-point • FIFO semantics • Unknown latency and buffering (fixed when system instantiated) RAMP Architecture, Language & Compiler

4. RAMP Target Model (2) • Transaction-style semantics for unit • Read 0/1 messages from each input • Perform some action • Write 0/1 messages to each output • Units MUST be latency insensitive RAMP Architecture, Language & Compiler

5. Target Model - Units Inside edge • Ports connect units to channels • FIFO signaling • Hardware or Software • Target cycle control • __Start • __Done • Allows for variable number of host cycles per target cycle RAMP Architecture, Language & Compiler

6. Target Model – Channel (1) • Channel semantics • Each channel carries arbitrary set of message types, statically determined • Ordered delivery • Debugging through monitoring & injection • Provides for cross-platform simulations RAMP Architecture, Language & Compiler

7. Target Model – Channel (2) • Channel parameters for timing-accurate simulations • Bitwidth (in bits per target clock cycle) • Latency (in target clock cycles) • Buffering (in either fragments or messages) • Fragments (one target clock cycle’s worth of data) • Smaller than messages • Convey the simulation time through idles RAMP Architecture, Language & Compiler

8. Timing Model Zero fragments still indicates passage of time Implement outside of the units Fragmentation Messages may be larger than fragments Channels carry (per target cycle): Zero or one fragments Between zero and one messages Target Model – Channel (3) RAMP Architecture, Language & Compiler

9. Target Model - Debugging Channel model + target time model supports: • Monitoring • All communication over channels can be examined and controlled • Single-stepping • Target time can be paused or slowed down • Simulation steering • Inject messages into channels • Mixed-mode emulation/simulation • Can move some units into software simulation • Cross-platform communication hidden by RDL compiler (RDLC) RAMP Architecture, Language & Compiler

10. Host Model • Cross-platform • Units implemented in many languages • Library units for I/O • Links implement channels • Links • Can be mapped to anything that transmits data (e.g.,FPGA wires, Ethernet, Carrier Pigeon) RAMP Architecture, Language & Compiler

11. Host Model – Wrapper (1) RAMP Architecture, Language & Compiler

12. Host Model – Wrapper (2) • Inside Edge • Wrapper provides this interface to unit • Clean, mostly free of implementation • Each host language needs language-specific version of interface • Outside Edge • Implementation dependant • Deals with physical links • RDLC generates the wrapper and all of the links • Uses plugins for easy extensibility to add new host languages or new link types RAMP Architecture, Language & Compiler

13. Host Model - Link • Typically Three Components • Packing & Unpacking • Timing Model • Physical Transport RAMP Architecture, Language & Compiler

14. RDL (1) • “RAMP Description Language” • General process network system description language • Compiler includes back-end extensibility • Links, other toolflows, external signals • Does NOT include or examine the functionality of leaf units! RAMP Architecture, Language & Compiler

15. RDL (2) • Hierarchical Namespaces • Declarations can be external to a namespace • Replaces “preprocessing” • Allows for communal development • RDL Target Constructs • Channels, Messages and Port types • Units include instances, inputs, outputs and connections • RDL Host Constructs • One platform per board or computer • Platforms include an implementation language • Hierarchy allows for, eg. A board with many FPGAs • RDL Mappings • Hierarchy allows for “compile one, run many” • Allows specific units and channels to be precisely mapped RAMP Architecture, Language & Compiler

16. RDL Example (1) • Up/Down Counter • Push button input • 4-bit LED output • Utility as example • Proof of concept • Simple language example • Hands on demo RAMP Architecture, Language & Compiler

17. RDL Example (2) unit { input bit[1] UpDown; output bit[32] Count; } Counter; RAMP Architecture, Language & Compiler

18. RDL Example (3) RAMP Architecture, Language & Compiler

19. RDL Example (4) unit { instance IO::BooleanInput BooleanInput; instance Counter Counter; instance IO::Display7Seg Display7Seg; channel fifopipe[1, 1, 1] InChannel { BooleanInput.Value -> Counter.UpDown }; channel fifopipe[32, 1, 1] OutChannel { Counter.Count -> Display7Seg.Value }; } CounterExample; RAMP Architecture, Language & Compiler

20. RDL Example (5) channel … InChannel { BooleanInput.Value -> Counter.UpDown }; instance IO::BooleanInput BooleanInput(InChannel); channel … InChannel; instance IO::BooleanInput BooleanInput(Value(InChannel)); channel … InChannel; RAMP Architecture, Language & Compiler

21. RDL Example (6) platform { language "verilog"; default link “RegisterLink"; engine “XUPEngine”; } XUP; map { platform XUP BasePlatformInst; unit CounterExample BaseUnitInst; } XUPCounter; RAMP Architecture, Language & Compiler

22. RDLC Toolflow Development Steps • Leaf-Unit Implementation • RDL unit descriptions • RDLC generates shell code in a specific language (Verilog, Java…) • Researcher adds implementation code • RDL system design • Specify connectivity between leaf units in target • Specify channel parameters (latency, BW, buffers) • Specify mapping of units and channels to host resources (FPGAs, comm links, …) • RDLC generates complete implementation code • Includes all links, instantiates all unit shells RAMP Architecture, Language & Compiler

23. RDLC Back End • Language Families • Hardware • Verilog – Completely finished • VHDL – Trivial addition • Bluespec planned • Software • Java in progress • C/C++ planned • RDL / UTL? • Your language here? RAMP Architecture, Language & Compiler

24. State of the Project • Working hardware implementation! • Compiled RDL to Verilog • Tested on a CaLinx2 and XUP Board • Java and BEE2 should be done before Feb 1, 2006 • RDL & RDL Compiler • RDL is stable • Some advanced features are in flux • Ready for use! • Working compiler, written in java • Powerful parser & output generators • Easily extensible • Software (Java) back end almost complete RAMP Architecture, Language & Compiler

25. Future Work • RDL & RDLC Features • Language Features • Generated code, port arrays and compile time parameters • Significant additions to back end • Languages, platforms, links • Debugging automation • Documentation • Architecture, Language & Compiler Technical Report • Complete compiler internals documentation • Automated Testing • Regression tests for the compiler • Automated test code generation for links and units RAMP Architecture, Language & Compiler

26. Website & Community • http://ramp.eecs.berkeley.edu • Planned Features • Wiki – Certainly not JSPWiki • CVS Repository • Mailing list control and archives • Communal project listings • Ideas, Comments & Requests • gdgib@berkeley.edu, CC: krste@mit.edu RAMP Architecture, Language & Compiler