R ECONFIGURABLE C OMPUTING F OR S PACE

1. RECONFIGURABLE COMPUTING FOR SPACE Team Reconfigurable Systems: Cameron Dennis, Chris Canine, Terseer Ityavyar Sponsored by Dr. Greg Donohoe and UI CAMBR Background Project Learning and Experimentation Still To Be Done • Goal • To highlight the benefits of using a differential serial communications scheme rather than a standard single-ended parallel system • Needs • Convince engineers at NASA and other research centers that implementing this type of system has distinct and noticeable benefits • Provide the documentation necessary to enable the implementation of this system • Specifications and Constraints • Transfer at least 800 Mbps of data from either of two transmitting nodes to either of two receiving nodes • Show the stability of the system with a Bit Error Rate Test giving no errors in a 15 minute period • Deliver documentation that provides a comparison of serial differential signaling vs. parallel single-ended signaling on the basis of: • Reduced Power Consumption • Reduced Circuit Board Area • Compared families of FPGAs on their features vs. cost and learning curve • Compared manufacturers of SerDes devices and crossbars based on data throughput and LVDS ability • For all components, the ability to program and test using a JTAG interface was preferable, but not required • Gathered cost data for all components • Discovered methods to: • Determine maximum signal speed • Implement Bit Error Rate and Eye Diagram tests • Calculate power consumption onboard and in simulation • Currently designing a serial communications prototype system • Experimenting with various data and clock encoding methods • Complete our serial comm. prototype • Complete the layout of the printed circuit board • Determine all final components needed, including onboard capacitors, resistors and voltage regulators • Fabricate the PCB • Testing of the PCB (BERR, Eye Diagram, Power) • Document the Cadence design flow System Architecture FPGA FPGA • Four FPGA Transmitters/Receivers • Xilinx Spartan IIE in PQ208 package • Four Serializer/Deserializers • National Semiconductor DS92LV16 • One 2x2 Crosspoint Switch • National Semiconductor SCAN90 • One LCD Display • Generic Display w/ HD44780 Control • One 50MHz Clock Crystal • SerDes may require additional crystal • Assorted Surface-mount Capacitors, Resistors and Voltage Regulators • Specific values will be determined after layout is completed and simulated • Assorted Connectors 16 16 SerDes SerDes 2 2 Crossbar 2 2 FPGA FPGA 16 16 SerDes SerDes 11 Clock LCD Display