1 / 24

Progress report of LDPC codes

Progress report of LDPC codes. Advisor : Tzi-Dar Chiueh Student : Hsiu-min Lin Date : Jan 3 th , 2005. Outline. Overview of LDPC and related application LDPC algorithm Optimum decoding Various Log Likelihood Ratio (LLR) introduction Simulation result LDPC architecture

menefer
Download Presentation

Progress report of LDPC codes

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Progress report of LDPC codes Advisor : Tzi-Dar Chiueh Student : Hsiu-min Lin Date : Jan 3th, 2005

  2. Outline • Overview of LDPC and related application • LDPC algorithm • Optimum decoding • Various Log Likelihood Ratio (LLR) introduction • Simulation result • LDPC architecture • Conclusion and Reference

  3. Properties of LDPC codes • One kind of Block Codes • H is sparse • Very few 1’s in each row and column • Variety of H (wr ,wc ) LDPC codes • That each row is of fixed weight wr and column is of fixed weight wc isregular • If not, that’sirregular. • Suppose a LDPC code is a (n,k) block code • H is a (n-k) x n matrix • (n-k) .wr = n.wc • Code rate = k/n = 1-wc/wr

  4. Tanner Graph • H can be represented by a Tanner graph • For a (n,k) code, it consists of n variable nodes and (n-k) check nodes • Each edge on the graph represents a nonzero entry in H check nodes variable nodes

  5. Cycle path • The number of 1’s in common between any two columns. • Short cycle effect • Girth concept.

  6. LDPC excellent performance • If block length is n , for large n practically all the LDPC codes in the ensemble have a minimum distance of at least n • It mean that The larger block length is, the better performance is • s is Wr and t is Wc

  7. LDPC in 802.3an progress • LDPC is used in IEEE 802.3an (10G Ethernet using twist pairs)[1]

  8. Candidate H in 802.3an [2]

  9. Outline • Overview of LDPC • LDPC algorithm • Optimum decoding • Various Log Likelihood Ratio (LLR) introduction • Simulation result • LDPC architecture and Reference • Conclusion

  10. Optimum decoding • Assuming received signals has n bits to find codeword , y= + , and each bit is independent , In order to compute the 0/1 probability of each

  11. Optimum decoding • is overall information of the bit n, • is the intrinsic information of the bit n • is the extrinsic information of the bit n ☆Optimum decoding with cycle free hypothesis is interconnection of nodes in Tanner graph. M(n) is final terminal node depending on distribution of 1 in H matrix.

  12. Optimum decoding (Cont) • Short cycle length and numbers effect would decrease performance obviously • Break short length by inserting new column (for ex: generate extending (14,8) hamming code instead of original (7,4)hamming code) • Optimum decoding could be applied for all block and convolutional code

  13. Log domain algorithm • Initialization: • Horizontal:[3] • Vertical:

  14. The variety of Log domain analysis • Horizontal processing stage has more flexibility (approximate) to trade off performance and complexity • LLR algorithm [4] • min-sum algorithm • min-sum-with-correction-factor algorithm

  15. Log domain simulation result

  16. Log domain algorithm implementation • LLR algorithm: • Usually use look up table or piecewise linear approximation to implement Implementation example: 1Gbps,690mW, code rate 1/2 ,1024 bit LDPC chip JSSCC(2002) [5] and Parhi “quasi-cycle overlap LDPC (IEEE trans on VLSI 2004)[6]

  17. Log domain algorithm implementation

  18. Outline • Overview of LDPC • LDPC algorithm • Optimum decoding • Various Log Likelihood Ratio (LLR) introduction • Simulation result • LDPC architecture • Conclusion

  19. Hardware Implementation issue • In circuit level, It is impossible to approach Shannon limlt.(0.0045db, block sizes is 10^7) • LDPC has better parallel processing property than Turbo codes. • Hardware architecture is divided into two categories. -Hardware sharing (Serial, memory based ): [6],[7],[8],[9],[10],[11] -parallel processing (Parallel, hardwire connection ) :[5] • The key critical implementation issue in LDPC is interconnect handling.

  20. LDPC Architecture proposed • Overlapped Message Passing for Quasi-Cyclic Low-Density Parity Check Codes[6]: • To find the rule decoder could overlap between horizontal and vertical processing for quasi-cycle LDPC family. • A Scalable Architecture for LDPC Decoding[9]: • Add the prefetcher to increase speed in memory based arhitecture and implement the specific algorithm called UMP[12]. • Low power VLSI Decoder Architecture for LDPC Codes[10]: • Use BJCR to decode instead of sum of product algorithm due to lower iteration number for power saving purpose.

  21. LDPC Architecture proposed (Cont) • Decoder-First Code Design[8]: • Reverse traditional decoder design concept and use suffle network to handle horizontal processing. • Design of VLSI Implementation-Oriented LDPC Codes[11]: • First find small code matrix H suitable for decoder design and then expand this matrix following certain rule. • Joint (3,k)-Regular LDPC Code and Decoder/Encoder Design[7]: • Inspired by [8] and girth concept, Parhi tries to design joint en/decoder design flow

  22. Conclusion and future work • All LDPC VLSI decoders use log domain algorithm to implement. • It seem to have less headroom to improve log domain algorithm since 2001. • In choice of LDPC architecture, memory based ones has more flexibility than parallel hardwired in recently years. • Continue to work on professor’s architecture, using feature has been published in papers.

  23. Reference • [1] Channel Coding for 10GBASE-T ,Mar. 2004 ,Katsutoshi SEKI, NEC Electronics, IEEE 802.3an task group. • [2] Performance evaluation of low latency LDPC code Sept 2004, Katsutoshi Seki, NEC Electronics, IEEE 802.3an task group. • [3] Iterative Decoding of Binary block and convolutional codes. By Hagenauer IEEE trans on Information theory 1996 • [4] Efficient Implementation of the sum-product algorithm for decoding LDPC Codes .by Xiao-Yu Hu, Evangelos Eleftheriou and Ajay IEEE 2001. • [5] A 690-mW 1-Gb/s 1024bits,Rate-1/2 Low-Density Parity-Check Code Decoder by Andrew J.Blanksby IEEE JSSC March, 2002 • [6]Overlapped Message Passing for Quasi-Cyclic Low-Density Parity Check Codes ,by Parhi,IEEE trans on VLSI system, June 2004. • [7] Joint (3,k)-Regular LDPC Code and Decoder/Encoder Design By Parhi , IEEE trans on signal processing ,April 2004 • [8] Decoder-First Code Design, By Emmanuel Boutillon, University of Tornondo.

  24. Reference (Cont) • [9] A Scalable Architecture for LDPC Decoding. Proceeding of the Design ,Automation and Test in Europe Conference IEEE 2004 • [10]Low power VLSI Decoder Architecture for LDPC Codes. By Mohammad M.Mansour 2002. • [11] Design of VLSI Implementation-Oriented LDPC Codes by Hao Zhong and Tong Zhang ,IEEE 2003 • [12] Reduced complexity iterative decoding of low density parity check based on belief propagation” by M.Fossorier IEEE trans on Comm

More Related