Reliability Enhancement via Sleep Transistors

1. Reliability Enhancement via Sleep Transistors Frank Sill Torres+, Claas Cornelius*, Dirk Timmermann* + Department of Electronic Engineering, Federal University of Minas Gerais, Belo Horizonte, Brazil * Inst. of Applied Microelectronics and Computer Engineering, University of Rostock, Germany

2. Focus / Main ideas • Approach for extension of expected lifetime • Application of simulation environment for MTTF estimation

3. Outline • Motivation • Preliminaries • Reliability Enhancement via Sleep Transistors • Simulation Environment • Results • Conclusion

4. Motivation Technology Development Gulftown 1.170 Mil. Probability for failures increases due to: • Increasing transistor count • Shrinking technology Wolfdale 410 Mil. Tecnology Yonah 151 Mil. Prescott 125 Mil. Northwood 55 Mil. Wolfdale 410 Mil.

5. Motivation Error classification Error Temporary Soft errors, Voltage drop, Coupling, … Permanent Reduced Performance Process variations, Electro-migration, Oxide wearout, NBTI, ... Malfunction Electromigration, Oxide breakdown ...

6. Preliminaries Power-Gating with Sleep Transistors • Very well-known and effective approach for leakage reduction • Insertion of sleep transistors (mostly with high-threshold voltage) between logic module and supply • Disconnection from supply during standby Sleep virtual VDD Logic block High-Vth virtual GND Sleep • M. Powell, et al., Proc. ISLPED, 2000. • A. Ramalingam, et al., Proc. ASP-DAC, 2005.

7. Preliminaries Time Dependent Failure Mechanisms • Electromigration (EM) • Performance reduction and errors • Depending on currentsand temperature • Negative Bias Temperature Instability (NBTI) • Performance reduction • Depending on voltage level and temperature • Time Dependent Dielectric Breakdown (TDDB) • Performance reduction and errors • Depending on voltage level and temperature Increase of lifetime through reduction of supply voltage and activity

8. Reliability Enhancement via Sleep Transistors Concept and Realization • Basic idea: Reduction of degradation via module deactivation • Problem: What to do at run-time? Module Module 1 Instance 1 Module tlife-system = tlife-module ≈ tlife-old +toff ≈ 2*tlife-old + tsleep Module 2 SLEEP MUX Module 1 Instance 2 tlife-new ≈ tlife-old + toff

9. Reliability Enhancement via Sleep Transistors Expectations • Lifetime • Increase by more than factor 2 (not linear relation between effective voltage and failure mechanisms) • Area • Increase by slightly more than factor 2 • Ca. 50 % less than Triple Modular Redundancy (TMR) • Power dissipation • Slight increase of dynamic power dissipation • Increase of leakage by ca. factor 2 • Delay • Slight increase through multiplexer delays

10. Reliability Enhancement via Sleep Transistors Comments • Application • Limited improvements for devices with long standby times (mobiles, home PCs) • High improvements for high availabilityapplications (server, aerospace equipment, mobile communication nodes) • Multiplexer • Problem: no deactivation of multiplexer • Solution: use of transmission gates (less vulnerable) • Control signals (for sleep transistor, multiplexer) • Logic for control signal generation must be reliable too • Hence: reliable implementation (HighTox, wire widening, …) • More research required

11. Simulation Environment • Desired: Simulative estimation of average time until first failure (also known as Mean Time To Failure – MTTF) • Solution: • Application of voltage controlled variable elements and parameters for failure modeling (xSpice, VerilogA, …) • Linear increase/decrease of control voltage at simulation time • Example: HSPICE model of transistor with TDDB and varying width V0 Vref 0 DC 1 V1 Vctrl 0 PULSE 1e12 0 0 1E-2 1E-9 1E1 2E1 M0 D G N1 0 nmos W='1e-7 * V(Vctrl)/V(Vref)' M1 N1 G S 0 nmos W='1e-7 * V(Vctrl)/V(Vref)' G1 G N1 VCR Vctrl 0 10

12. Results Mean Time To Failure (MTTF) 2.2 (BPTM 22nm, 100 samples, TDDB and EM modeling, basic MTTF of 300 clock cycles, relaxed timing, w/o temperature consideration)

13. Results Delay / Power / Area Average values: Delay: + 7 %, Power: + 5 %, Area: + 110 %

14. Conclusion • Progressing susceptibility of current technologies against severe failure mechanisms • Extension of expected lifetime by alternating (de-)activation of redundant blocks via sleep transistors • Environment for simulation of time-dependent degradation of design components • Increase of MTTF by morethanfactor2 through proposed approach • Factor 1.2 for relation of average increase of MTTF and area • Future tasks: • Application of selective redundancy techniques • Merging with approaches on system level • Analysis of control logic

15. Thank you!franksill@ufmg.brclaas.cornelius@uni-rostock.de

16. Motivation Time-Dependent Dielectric Breakdown (TDDB) • Tunneling currents Wear out of gate oxide • Creation of conducting path between Gate and Substrate, Drain, Source • Depending on electrical field over gate oxide, temperature(exp.), and gate oxide thickness (exp.) • Also: abrupt damage due to extreme overvoltage (e.g. Electro-Static Discharge) Source: Pey&Tung Source: Pey&Tung

17. Reliability Enhancement via Sleep Transistors Realization

18. Reliability Enhancement via Sleep Transistors Blocks / Requirements

19. Simulation Environment Overview

20. Simulation Environment Error Modeling