Modern Floorplanning Based on Fast Simulated Annealing

Modern Floorplanning Based on Fast Simulated Annealing Tung-Chieh Chen* and Yao-Wen Chang*# Graduate Institute of Electronics Engineering* Department of Electrical Engineering# National Taiwan University, Taipei, Taiwan April 5, 2005

Outline • Introduction • Fast simulated annealing scheme • Fixed-outline floorplanning • Bus-driven floorplanning • Conclusion

Introduction • Popular modern floorplanning constraints • Fixed-die (fixed-outline) constraint • Block positions and interconnect constraints • Two types of modern floorplanning problems • Fixed-outline floorplanning (FOF) • Bus-driven floorplanning (BDF) • Need to consider the interconnect and block positions simultaneously. • Our floorplanner is based on • the B*-tree floorplan representation and • a fast three-stage simulated annealing scheme, called Fast-SA.

Previous Work • Fixed-outline floorplanning (FOF) • Adya et al. (ICCD 2001) -- Parquet • Present new moves to guide local search. • Lin et al. (ASPDAC 2004) -- GFA • Use evolutionary search. • However, both success rates are not high enough when whitespace is small. • Bus-driven floorplanning (BDF) • Rafiq et al. (ISPD 2002, ISCAS 2002) • The bus is composed of wires connecting only two blocks. • Not general for real bus designs. • Xiang et al. (ICCAD 2004) • General BDF allows a bus to connect multiple blocks. • Use the sequences pair (SP) representation.

Our Contribution • Propose a fast three-stage simulated annealing scheme (Fast-SA). • For the fixed-outline floorplanning (FOF) • Propose a new objective function and an adaptive Fast-SA. • Obtain much higher success rates. • For the bus-driven floorplanning (BDF) • Explore the feasibility conditions of the B*-tree with the bus constraints. • Reduce 20% (50%) dead space on average for the floorplanning with hard (soft) blocks, compared with the most recent work by Xiang et al.

n0 b5 b6 b9 b3 n7 n1 b1 b4 b2 x1 = x0 n8 n2 n5 b0 b8 n9 n3 n6 b7 n4 (x0, y0) w0 x7 = x0 + w0 B*-Tree Floorplan Representation • Chang et al., “B*-tree: A new representation for non-slicing floorplans,” DAC-2k. • Given a B*-tree, the legal floorplan can be obtained in amortized linear time. • Left child: the lowest, adjacent block on the right (xj = xi + wi). • Right child: the first block above, with the same x-coordinate (xj = xi). The corresponding B*-tree A compacted floorplan

Simulated Annealing (SA) Using B*-trees • Non-zero probability for up-hill climbing: p = min{1, e-ΔC/T} • Perturbations (neighboring solutions) • Op1: Rotate a block. • Op2: Move a node/block to another place. • Op3: Swap two nodes/blocks. • Op4: Resize a soft block. • The cost function is basedon problem requirements.(fixed-outline constraint, bus constraint, etc.)

Simulated Annealing Schedule • Classical annealing schedule • Classical temperature updating function, λis set to a fixed value (0.85 as recommended by most previous work) Tnew = λTold, 0 < λ< 1 • TimberWolf annealing schedule (Sechen and Sangiovanni-Vincentelli, DAC-86) • Increase λ gradually from its lowest value (0.8) to its highest value (approximately 0.95) and then gradually decreases λ back to its lowest value.

Classical SA TimberWolf SA Fast-SA Temperature III I II Cost Time Time Time S (a) (b) (c) local optima global optimum State (Solution space) Fast Simulated Annealing (1/2) • Reduce the number of “up-hill” moves in the beginning • Consists of three stages • The high-temperature random search stage • The pseudo-greedy local search stage • The hill-climbing search stage • Comparisons for the temperature vs. search time: Probability for up-hill climbing: p = min{1, e-ΔC/T}

Fast Simulated Annealing (2/2) • Temperature update • If is large, the temperature decreases slowly. • If is small, the temperature decreases quickly. The temperature for nth iteration Average uphill cost Initial acceptance rate Average cost change since the SA started User-specified constants P k,c

Convergence and Stability for Fast-SA • Classical SATimberWolf SAFast-SA, k=1 (no greedy local search)Fast-SA, k=7 • Ran the circuit n100 for 10 times. • Fast-SA has better convergence speed than TimberWolf SA and classical SA. Classical SA TimberWolf SA Fast SA (no greedy local search) Fast SA

R*=2 Γ=0.50 R*=1 Γ=0.15 H* H* W* W* Fixed-Outline Constraints • Two user-specified parameters: • Γ:maximum white-space fraction,and • R*: desired aspect ratio (height/width) • The outline (height H* and width W*) is defined by: • Use the same formulation as Adya et al. (ICCD-2001).

Cost Function for Fixed-Outline Floorplanning • Cost for a floorplan F A Chip area Area weight W Wirelength Wirelength weight R* Desired aspect ratio R Current floorplan aspect ratio Chip area Wirelength Aspect ratio penalty

Adaptive Simulated Annealing • Best aspect ratio of the floorplan in the fixed outline is not the same as that of the outline. • Shall decrease the weight of aspect ratio penalty to concentrate on the floorplan wirelenth/area optimization. • An adaptive method to control the weights in the cost function is used according to n most recent floorplans found. • The more feasible floorplans, the less aspect ratio penalty. Decrease aspect ratio penalty (a) (b)

Exp: Fixed-Outline Floorplanning (1/2) • Success rate vs. aspect ratio on circuit n100 Γ=10% Γ=15% • On a Pentium 4 1.6GHz PC

Exp: Fixed-Outline Floorplanning (2/2) • Wirelength optimization under the fixed-outline constraint. • Obtain 20% less wirelength on average, reduce 55% runtime on average, compared to Parquet. • On a Pentium 4 1.6GHz PC

Fixed-Outline Floorplanning Results Circuit: ami49 Circuit: n100

Outline • Introduction • Fast simulated annealing scheme • Fixed-outline floorplanning • Bus-driven floorplanning (BDF) • Conclusion

BDF Problem Formulation • Given n rectangular macro blocks B = { bi | i= 1, …, n }and m buses U = { ui | i = 1, …, m }, each bus uihas a width tiand goes through a set of blocks Bi. • Decide the positions of macro blocks and buses, and bus uigoes through all of its blocks. • Minimize the chip/bus area. • No overlap between any two blocks or between any two horizontal (vertical) buses. • A feasible horizontal bus u = < H,t, { A, B, C }>. • ymax = yc + hc • ymin = yb • ymax - ymin≥ t

B*-trees Properties for Bus Constraints (1/4) • Left child • The lowest, adjacent block on the right (xj = xi + wi) Property 1: In a B*-tree, the nodes in a left-skewed sub-tree may satisfy a horizontal bus constraint. n0 b5 b6 b9 n7 n1 b3 b1 b4 b2 n8 n2 n5 b0 b8 n9 n3 n6 b7 n4

B*-trees Properties for Bus Constraints (2/4) Property 2: Inserting dummy blocks of appropriate heights, we can guarantee a horizontal bus with blocks whose corresponding B*-tree nodes are in a left-skewed sub-tree

B*-trees Properties for Bus Constraints (3/4) • The height of the dummy block Di: • An example of inserting dummy blocks to satisfy a horizontal bus.

B*-trees Properties for Bus Constraints (4/4) • Right child • The first block above, with the same x-coordinate (xj = xi). Property 3: In a B*-tree, the nodes in a right-skewed sub-tree can guarantee the feasibility of a vertical bus.

Infeasible Twisted-Bus Structure • Consider two buses simultaneously, we cannot always fix the horizontal bus constraint by inserting dummy blocks. • Should discard such a tree configuration. u1 = {b0, b3} u2 = {b2, b6}

Bus-Overlapping • Use dummy blocks to avoid bus-overlapping while considering multiple buses. u1 = {b0, b4} u2 = {b2, b3} u1 = {b0, b4} u2 = {b2, b3}

Our BDF Algorithm (1/2) • Use simulated annealing to search for a desired solution. • Cost of a floorplan F, buses U: A chip area B bus area M number of unassigned buses

Our BDF Algorithm (2/2) Initialize floorplan Perturb and pack “Twisted-bus structure” exists? yes no Adjust heights of dummy blocks Simulated annealing iterations Pack and decide bus location Compute floorplan cost (quality) Cooling down Report the best floorplan

y y T3 B3 b5 b4 b4 b5 b3 b3 b0 b0 b1 b2 b1 b2 x x L3R3 (a) (b) Soft Macro Block Adjustment • Key: Line up with adjacent blocks • Each soft block has four candidates for the block dimensions. • Advantage: fast and reasonably effective • Similar idea by Chi et al., Chung Yuan Journal, 2003. R3

Exp: Bus-Driven Floorplanning • MCNC benchmark on Pentium 4 2.8GHz. Obtain 20% (55%) less dead space on average for hard (soft) macro blocks. *SP: Hua Xiang, Xiaoping Tang, and Martin D.F. Wong, “Bus-driven floorplanning”, ICCAD 2003. The platform of SP is Intel Xeon 2.4GHz.

BDF Result • MCNC ami49-3 with soft block adjustment. • It has 49 macro blocks and 15 buses.

Conclusion • Have proposed algorithms for the modern floorplanning problems with fixed-outline constraints and bus-constraints based on the new Fast-SA scheme. • Have shown Fast-SA leads to faster and stabler convergence to desired floorplan solutions. • Have shown the efficiency and effectiveness of our floorplanning algorithms for fixed-outline/bus-driven floorplanning.

B*-tree 2005 will be available soon athttp://eda.ee.ntu.edu.tw/research.htm B*-tree 1.0 (year 2000) + new perturbations + Fast-SA Thank you for your attention!

Modern Floorplanning Based on Fast Simulated Annealing