CPU: software architecture

1. CPU: software architecture

2. General Introduction INSTRUCTION SET (PART 1)

3. General Introduction (1/5): On Instructions • Instruction operate with data or with the flow of the program • The following information is absolutely needed to define an instruction: • OpCode: What is the operation to be done • Operands: What operands are involved • Addressing mode: Where is data to be found • Additional information may include size of operands or other modifiers.

4. General Introduction (2/5): On instructions • The number and type of instructions, i.e., what they do, depend on the MCU or MPU family and model. • Several types of instructions are found in almost any MCU or MPU • Syntax may be different • An instruction set is not necessarily independent • It may happen that the operation of one instruction may be realized with other with proper operands.

5. General Introduction (3/5): On operands • The maximum number of operands of instructions depends on MCU or MPU model • Most small microcontrollers work with two operands. • Some specific families work with three operands • In many instances, one or more operands may be implicit • Two operands (data) are considered: destination and source

6. General Introduction (4/5): Destination • The result of an instruction, except for some cases, is stored either as a • CPU register content • memory cell (or cells, depending on data size) contents • contents of register of an IO device. • The place where the result is stored is called destination (dest)

7. General Introduction (5/5): Source • The source is the other operand involved in the operation • It may be a • Constant data or a • CPU Register, memory cell(s) or IO register contents • Abusing of language, source is referred to as • The source itself alone • An expression that involves the source and destination (as in source + destination) • An expression that includes the source and other information

8. Register Transfer Notation (RTN) • The register transfer notation (RTN) is a symbolic, MCU independent notation to indicate CPU transactions, operations in programs, etc. Arrow points to destination: • dest  src • In an expression such as dest  dest + source, the destination data in “dest + source” is the one previous to the transaction, and “dest” on the left is the data after transaction • PC  NewAddress is mentioned as “Jump to NewAddress” or “ GOTO Newaddress”

9. Hybrid RTN and convention (1/3) • Convention: When RTN is too complicated, a simple sentence is preferred • Jump to address, instead a PC  address • Operands are denoted as follows: • For a CPU register, the register name is given . • In MSP430: R4, R5, etc. • INTEL 8086: AX, AH, BL, etc. • In general, simply register Reg X, or RX • A constant data by the number or #number • Example R6  34h, or R6 #34h means R6 is stored with number 34h

10. Hybrid RTN and convention (2/3) • When data is to be stored in memory, or IO device register, the address at memory is provided in parenthesis or preceded by &. • (2030h) denotes data at address 2030h • (Hello) denotes data at address defined by a label named Hello . • (R5) denotes data at address given by contents of register R5 • (R5 + X) denotes data at address given by the result of adding X to the contents of register

11. RTN Conventions (3/3) • Data to register pertaining an I/O subsystem device: same notation as in memory, except that address belong to the Device register, and it must be indicated. Usually, use the name of the register • (P1OUT) denotes the address of Output Register of Port 1 • (WDTCTL) denotes the address of the Watchdog Timer Control Register • Addresses are also denoted with & (loan from C) • (2030h) same as &2030h • (P1OUT) same as &P1OUT

12. Machine Language • Machine language instruction is the set of n-bit words that define an instruction • If there are more than one word, the first in the set is called instruction word • The instruction word contains: • OpCode: field of bits that define the operation • Destination and Source bit fields • Addressing Mode field: That define how and where to read data, destination and source fields.

13. Example: MSP430 instructions 0

14. From machine to assembly (1/2) • Assembly language makes programming “in machine language” much easier and direct • Each machine language instruction is associated to one and only one assembly language instruction • Converting an assembly language to its machine language version is “to assemble” . • The software tools to assemble are • assembler : works all instructions before assembling • Interpreter or line interpreter : works with an isolated instruction • “To disassemble” is to translate the machine instruction into assembly instruction

15. Example Opcode Name: add Operand size: word add.w datum Source info: immediate add.w # 480d Destination Register mode: add.w #480Dh,R13

16. From machine to assembly (2/2) • An assembly language instruction consists of • A mnemonics: Name given to the opcode, • Operands written in a specific syntax for addressing mode • The specific syntax for mnemonics, operands and order in the instruction is CPU family dependent. • The three examples below all express an instruction of the form dest (0204h), dest is a CPU register and the data size is a byte • MSP430 mov.b 0204h, R6 (CPU register is R6) • Intel 8086 mov AH, [0204h] (CPU register is AH) • M68CH11 LDAA $0204 (CPU register is accumulator A)

17. Instruction Types Instruction set (Part 2)

18. Instruction Types (1/2) • Data transfer instructions (dest  src) • For reading and writing to and from memory and IO registers, Storing with data, copy from registers. • These instructions in general do not affect flags • Arithmetic and logic operations • Of the type dest dest * src (* means an operation), with flags being or not affected • Of the type (dest*src), affecting only flags

19. Instruction Types (2/2) • Register operations: manipulates bit order • Shift, roll and rotation • Flow program operations: On execution, they modify the content of the PC register • Jump instructions (PC  New Address) • Subroutine instructions: • Call and Return • Interrupt instructions: • Return from Interrupt.

20. Transfer operations (1/2) • Move instructions: copy source data onto destination data (dest src) • MSP430 mnemonics mov, mov.w, mov.b • Also called “load”, “store” instructions • Input and output transfer instructions • For those MCU with IO mapped IO systems • Input*: dest  (Input Port) • Output*: (Output port)  Source

21. Common Data Transfer Instructions • Stack transfer operations, managed by SP register (explained later) • Push: (TOS) src • Pop or Pull: dest  (TOS) • TOS means Top Of Stack • Swap: dest  source (exchange of contents; both operands are erased and reloaded)

22. Arithmetic instructions (1/2)Addition and Subtraction • Addition Operations: • Addition: dest  dest + src • Addition with carry: dest  dest + src + CFlag • Subtraction Operations: Usually with two’s complement addition • Subtraction: dest  dest – src • Subtraction with borrow : • dest  dest – src – BF for dual Carry/Borrow cases • dest  dest + NOT(src) + CF, when CF=0 denotes borrow • Compare operation: dest – src; only flags affected

23. Arithmetic instructions (2/2)Multiplication and division • Not all microcontrollers’ ALU’s implement these operations. • Operands and destination sizes are of outmost importance. • When not supported, these operations are done by software • Special cases are dedicated peripherals.

24. Logic InstructionsGeneral introduction • Bitwise and not bitwise • Most microcontrollers support only bitwise logic operations • Non bitwise logic operation principles: • Yield a boolean result (usually in a flag) • In source, “1” means operand is not zero; “0” means operand is zero • Used mainly in high performance systems or as part of “high level” instructions

25. Bitwise Logic Operations (1) • dest  dest*source means dest(j)dest(j)*source(j) • Bitwise operations permit individual bit manipulations • The source is usually called “mask” • “1”s in mask indicate which bits are to be affected • AND: dest  dest .AND. src • OR: dest  dest .OR. src • XOR: dest  dest .XOR. Src • NOT: dest  NOT(dest)

26. Bit manipulation : CLEAR 0.AND.X=0; 1.AND.X=X To clear specific bits in destination, the binary expression of the source has 0 at the bit positions to clear and 1 elsewhere Instruction in MSP430: BIC.B #00010010b,R6 0 0 0 1 0 0 1 0 R6

27. Bit manipulation : CLEAR 0.AND.X=0; 1.AND.X=X To clear specific bits in destination, the binary expression of the source has 0 at the bit positions to clear and 1 elsewhere Instruction in MSP430: AND.B #00010010b,R6 R6

28. Bit manipulation : TEST 0.AND.X=0; 1.AND.X=X To clear specific bits in destination, the binary expression of the source has 0 at the bit positions to clear and 1 elsewhere Instruction in MSP430: BIT.B #00010010b,R6 0 0 0 1 0 0 1 0 R6

29. Bit manipulation : SET To set specific bits in destination, the binary expression of the source has 1 at the bit positions to set and 0 elsewhere 0.OR.X=X; 1.OR.X=1 MSP430: BIS.B #00010010b,R6

30. Bit manipulation : TOGGLE To toggle specific bits in destination, the binary expression of the source has 1 at the bit positions to invert and 0 elsewhere 0.XOR.X=X; 1.XOR.X=X’ MSP430: XOR.B #00010010b,R6 XOR.B #68,R6 REG R6

31. Register operations:Shifts, rolls and rotates • Shift (or roll) right logically: • 0 dest(N-1)dest(N-2)  ….  dest(1)  dest(0)  CF • Shift left: • C dest(N-1)  dest(N-2)  ….  dest(1)  dest(0)  0 • Shift (or roll) right arithmetically: • Dest(N-1) dest(N-1)dest(N-2)  ….  dest(1)  dest(0)  CF • Rotate right through: • CFolddest(N-1)dest(N-2)  ….  dest(1)  dest(0)  CF

32. Shift and rotate examples

33. Program Flow Instructions (1)Jumps or Branch -- • ACTION: PC  NewAddress • Unconditional jumps: (jmp) • GOTO!!!!!!!!!!! Ohhhhhhh!!!!!! • Conditional jumps: test a flag condition • Basic tools for decisions

34. Conditional jumps (simple flags)

35. Example 1: Delay loop

36. Example 2: Repeat process N times Counter  N Label: Do process counter  counter -1 Jump if not zero to Label

37. Examples of composed Conditional Structures using basic structure • Single Flag(s) condition Instruction affecting flags FLAG? Instruction affecting flags Yes No FLAG_A? No • Multiple Flags: FLAG_A AND FLAG_B • Multiple Flags: FLAG_A OR FLAG_B Yes Instruction affecting flags FLAG_B? Yes No FLAG_A? Yes No FLAG_B? Yes No

38. Drawing for “low level”: If sentence (1) Inst. affecting flags A true? NO Yes Block B (NO forces jump)

39. Other names and otherConditional jumps To be used after a compare operation A-B, for numeric decisions)

40. Remarks on jumps • A jump is also called a “branch instruction” • Unconditional jumps are present in almost any CPU • Not all conditional jumps are necessarily present in the CPU architecture • The use of jumps is indispensable to devise non sequencial programs.

41. Subroutines and Procedures • Subroutines (also called functions or procedures) are pieces of executable code written and stored apart from the main code • They are to be executed when invoked from main code or other subroutine, but flow must return to original “normal” flow • The Address of first instruction is called Entry Address

42. Subroutine Instructions: • Call instruction: Saves the present value of the PC register and then loads the PC with the entry address of the subroutine • a) (TOS)  PC • PC  Sub. Entry Address • Return instruction: Retrieves the address following the call in the main code [PC  (TOS)] • Important note: Subroutine programming must ensure that return is well done

43. Subroutine process • Just before CALL execution PC points to next memory location after CALL. • Upon execution, the content of PC is pushed onto stack, and PC loaded with address of subroutine entry line 3. Subroutine is executed until instruction RET (return) is found. 4. Execution of RET pops PC, restoring the address of the instruction just after CALL --- This happens every time CALL is executed Important remark: Subroutine must be designed so that when RET is encountered SP is pointing to the right location

45. Call and Return E420 Return --- - Inst Bla bla F24A Next Instr. E402 - - - - - - - - F248 CALL SUB Entry Addr E400 Entry line Before Fetch of call: PC = F248 First step of execution: PC = F24A, (TOS) = F24A After return: PC = F24A After decode of call, and before execute phase: PC = F24A Second Step of Execution PC = E400 (TOS) = F24A

46. STACK and Stack Pointer

47. Stack Definition and Characteristics • Stack is a specialized memory segment which works in LIFO (Last In-First Out) mode. Managed by the Stack Pointer Register (SP) • Hardwired stack: physically defined, cannot change • Software defined: First address in stack defined by initialization of SP (by user or by compiler) • Stack Operations: • PUSH: storing a new data at the next available location • POP or PULL: retrieving last data available from the sequence (to be stored in some destination) • Important Note: A retrieved data is not deleted, but cannot be retrieved again with a stack operation • Top of Stack (TOS): memory address used in the stack operation (different for push or pop)

48. Basics of stack operation Empty at start (Only garbagge) X x x x x x x x x x Push TOS

49. Basics of stack operation PUSH (garbage not shown) D0 Push TOS Pop TOS

50. Basics of stack operation PUSH D0 D1 Push TOS Pop TOS