G.709 Frame Switching FAU-Prototype

1. G.709 Frame SwitchingFAU-Prototype L.Dembeck, W.Lautenschläger, J.Wolde, 14.06.05

2. Basic Node Architecture • Aggregation of client packets into equally sized containers: G.709 frames • Frame Aggregation Unit at network ingress and egress • Switching of each individual G.709 frame • Connection oriented labeling and bandwidth reservation • Continuous G.709 OTUx connections on transmission links

3. Role of FAU: classify client packets into destination and service classes aggregate homogeneous packet classes into frames forward the frames Position of FAU: any switching can be moved out 1:1 mapping of ports FAU is a specific line card of a frame switch Role and Position of the FAU

4. FAU Key Components • The following key components were defined based on the general specification: • FPGA • Performs all of the data processing • Serial high-speed I/O • SERDES functionality for line as well as matrix interface • Memory • Buffering of G.709 frames

5. FAU Test Board Concept ALCATEL Test Board RAM FPGA MSA300 interface MSA300 interface O / E / O SERDES SERDES O / E / O RAM XILINX RocketPHY Board

6. FAU Test Board Realization • FPGA • XILINX Virtex-IIPro FPGA (XC2VP100) • SRAM based configuration • 44k slices with 88k Flip-Flops and 8 Mbit embedded Block RAM capacity • Multiple I/O standards for all of the up to 1164 user pins • 0,13 µm technology with 9 layer copper process • 1,5 V core voltage • Serial high-speed I/O • XILINX RocketPHY Evaluation Board • Use of XILINX RocketPHY SERDES on a XILINX board • Up to 10.7 Gbit/s operation • Standard MSA300 connector to host board • RAM • DDR SO-DIMM

7. Board Design Issues • Challenges • High pin / trace counts • Impedance controlled traces • Test PCB • Double EURO-format • 20 layers • Buried vias • Blind vias

8. Board Design Results • Bottom view • G.709 interfaces • Top view • FPGA + RAM • Power supply • Programming i/f, EEPROM

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