Programma di attivit à e preventivo di spesa 2014 Sezione di Pavia

1. PixFEL Enabling technologies, building blocks and architectures for advanced X-ray pixel cameras at FELs Programma di attività e preventivo di spesa 2014 Sezione di Pavia INFN Pavia, Consiglio di Sezione, 9 luglio 2013

2. PixFEL project Goal of the project: investigating the technologies, designing the fundamental microelectronic building blocks and exploring the readout architectures for high performance X-ray imaging instrumentation to be be used in the experiments at the next generation free electron laser facilities • active edge pixel sensors, low density TSVs • 65 nm CMOS technology for front-end and readout electronics • in pixel data storage and readout architectures Duration: 3 years Participating INFN groups • INFN Pavia • INFN Pisa • INFN Trento (gruppocollegato) 2

3. People INFN Pavia: INFN Pisa: 2.4 FTE (resp. loc.: Giuliana Rizzo) INFN Trento (PD): 2.4 FTE (resp. loc.: Lucio Pancheri) 3

4. Main features of FELs FELs emit high intensity beam of ultrafast X-rays • energy range: 100 eV to 10 keV (l from 10 nm to 0.1 nm) • pulse duration: tens of femtoseconds to picoseconds • repetition rate: 100 Hz (continuous mode) to 5 MHz (burst mode) 4

5. Beam-line structure and pulse spacing Beam-line structure @Eu-XFEL Beam lines with different photon energies available at each facility Very different beam structure from one FEL facility to the other – some pose very challenging requirements on the instrumentation Eu-XFEL NGLS 5

6. Science program The science base accessible at FELs is quite broad • structural biology: study and solve the structures of large macromolecular biological systems • chemistry: understand the mechanisms of catalytic processes responsible for efficient conversion of light into electrical/chemical energy • material science: study the mechanisms of transport and storage of on increasingly smaller lengths and at faster time scales; • atomic and molecular science: is concerned with the study of fundamental interactions among electrons, between electrons and nuclei and between light and matter 6

7. Instrumentation Although ach experiment at FELs may require a specific detection system, two main scientific case may be identified • energy sensitive detectors with Fano limited energy resolution for spectroscopic experiments, possible position sensitivity for angular dispersive experiments (0D or 1D) • silicon drift detectors • high-Z detectors • cryogenic detectors • area detectors for imaging experiments, based on X-ray diffraction (2D) • charge coupled devices • hybrid pixel detectors • monolithic active pixel sensors 7

8. Long term goal of the collaboration Develop a four-side buttable module for the assembly of large area detectors with no or minimum dead area to be used at FEL experiments Good efficiency up to 10 keV 9 bit resolution (effective), 5 MHz sample rate wide dynamic range (1 to 10000 photons), single photon sensitivity burst and continuous mode operation 8 1 kframe

9. Aim of the PixFEL project Investigating the enabling technologies for the design of chips with minimum dead area and high functional densities • standard and slim edge sensors • vertical integration for double tier design of the front-end • low density TSVs for chip interconnection to the hybrid board • interposers for sensor to front-end pitch adaptation Studying, designing and testing the building blocks (CMOS 65 nm) for the front-end electronics, complying with the application requirements • low noise, (reconfigurable) wide input range front-end channel with dynamic compression, single photon detection • 9 bit (effective), 5 MS/s ADC (successive approximation register) • circuits for gain calibration Looking into architectures for fast chip operation and readout • frame storage mode (memory cell, maximum memory size, readout) • continuous readout mode (maximum speed, accounting for DAQ limitations) • reconfigurability (impact on the performance) 9

10. Work Packages WP1: Enabling technologies (Lucio Pancheri, UNITN and INFN TN) – will investigate the technologies with potential to enable the fabrication of advanced 2D X-ray imagers to be used at FELs; the activity will mainly focus on active edge pixel sensors and low density through silicon vias, as the most important processes for the fabrication of a four-side buttable chip. WP2: Building blocks (Massimo Manghisoni, UNIBG and INFN PV) – will address the design of the fundamental building blocks for the readout of a pixel detector in a 2D X-ray imager to be operated at FELs, and concentrate on the development of individual stages and with their integration in a single tier 8×8 matrix at first, and with the design of a 32×32, single tier matrix to be interconnected to a fully depleted pixel sensor in a later phase of the WP WP3: Architectures and testing (Stefano Bettarini, UNIPI and INFN PI) – will deal with a two-phase task: study of the readout architecture for the X-ray imager front-end chip; development of the hardware and software test systems and the placement of the final characterization of the detector in a beam line 10

11. Enabling technologies for a 4-side buttable module • Active edge pixel sensors were proposed to minimize the gap between the active area and the edge of the detector; key steps • trench etching • trench polisilicon filling • support wafer removal • Thickness ≥450 um needed for good efficiency @10 keV Low density TSVs for chip to PCB bump-bonding 11

12. Building blocks To be designed and fabricated in a 65 nm CMOS technology Wide dynamic range front-end channel • possible solution: use the non-linear features of MOSFET capacitors to dynamically change the gain with the input signal amplitude 9 bit (guarantees single photon resolution at small signal, small quantization noise in Poisson-limited regime), 5 MHz sample rate (for operation at the Eu-XFEL) SAR ADC 12

13. Readout architectures No sparsification technique can be applied to imaging detectors  a large amount of data needs to be read out in a relatively short amount of time, also depending on the structure of the X-ray beam Burst mode operation: data need to be stored locally and read out in the interval between two bursts; 65 nm CMOS technology is supposed to guarantee enough density to exceed the state-of-the-art of present FEL instrumentation in terms of storage capacity Continuous operation: data are read out as soon as they are collected, frame by frame; the relatively low repetition rate (~100 Hz) foreseen in FELs operated in continuous mode makes direct readout of a megapixel detector a task within reach of present technology The capability of switching from one mode of operation to the other may be an important asset for a 2D imager 13

14. Synergies with other experiments/projects In the framework of the WP3 (Microelectronics and Interconnection Technologies), the AIDA project is exploring 3D technologies for applications to radiation detection systems - in the same framework, people are developing microelectronics blocks in advanced technologies (including CMOS 65 nm) for chips to be interconnected by means of 3D processes The CMS and ATLAS collaborations have started a joint R&D activity to develop the next generation pixel detectors for the experiments at the HL-LHC - front-end design is mostly based on 65 nm CMOS technology The CMS collaborationis starting a research activity for the development of a momentum discriminating tracker for the CMS experiment at the HL-LHC - the design of the front-end chip will be based on the 65 nm CMOS technology adopted at CERN The investigation of radiation hardness issues at very high integrated doses (of the order of 1 Grad), which is pursued by the CMS collaboration in view of the luminosity upgrade of the LHC machine, is of relevance to the X-ray detector applications at FELs. 14

15. Workplan 2014 • define chip specifications. • design of test structures with single blocks (analog front-end, ADC, circuits for gain calibration, single MOS capacitors, I/O circuits), CMOS 65 nm • design of a 8x8 matrix, 100 um pitch • design of standard pixel sensors • start investigation on readout electronics 2015 • test the structures from the first run • start investigation on 3D integration processes, including low density TSVs • design of the 32x32 matrix (accounting for low density TSVs) • design of slim edge pixel sensors • interconnect the front-end chip to the (slim edge) pixel sensor • start writing VHDL and design some elementary digital block (memory cells, buffers) • start organizing the test beam 2016 • test the 32x32 front-end chip • test the chip after interconnection with the detector (demonstrator) • test the structures including low density TSVs (demonstrator) • complete VHDL design of the readout electronics (demonstrator) • test the chip on a beam 15

16. Three-year budget request 16