Fishbone: A Block-Level Placement and Routing Scheme

1. Fishbone: A Block-Level Placement and Routing Scheme Fan Mo and Robert K. Brayton EECS, UC Berkeley

2. Outline • The block level placement and routing problem • Routability, predictability • Fishbone scheme • Spine net topology • Base/Virtual pin pair • Row/column routing with left-edge algorithm • Integrated placement and routing • Experimental results • Discussion

3. Block-Level P&R • In conventional design flow, the block-level placement and routing are two sequential stages. • During placement, certain net model (fast but inaccurate) is used to estimate wire length, congestion, etc. • During routing, blocks are fixed and nets are routed with certain net model (slow but accurate). • Problem occurs when wrong estimation was made during the placement, or even early steps of the routing.

4. RST and HP • Rectilinear Steiner Tree (RST) • Smallest wire length • Slowest computation • Half-Perimeter Model (HP) • Good estimation of RST • Faster computation • Strictly speaking, HP is not a net topology. It cannot be used to predict congestion and routability • A common approach is to use HP in placement and RST in routing.

5. Block-Level Design in Reality • Pins of the blocks lie on layer mB. Routing takes place on a couple of higher metal layers, mB+1 and mB+2. • Layers mB+1 and mB+2 have preferred routing directions (vertical or horizontal) for better manufacturability. • Routability problem may occur, especially in and around pin regions. • Pins of a block may lie close to each other • Pins of adjacent blocks may lie close to each other. • Such routability problems are quite local, which are hard to predict even in the global routing step.

6. The New Routing Scheme • We want a net topology and a routing scheme that have • Better predictability of routability than HP (or even RST), especially in and around pin regions. • Faster computation than RST.

7. Spine Topology • The output pin of a net is on a vertical wire called "trunk"; and all the input pins connect to the spine by horizontal "branches". • Given pin positions, the net shape is fully determined. • Pin-pin distance is Manhattan. • Routability is easy to detect, given all pin positions.

8. Grids, Columns and Rows • The routing grids are given cyclic indices labeled 0,1,2,…, GR-1, where GR is the grid radix. • The whole routing space is composed of rows (or columns), each containing grid 0~GR-1.

9. Base Pins GR=6

10. branch trunk virtual input pin (mB+1) virtual output pin (mB+2) Virtual Pins GR=6

11. Base/Virtual Pin-Pairs GR=6

12. The Fishbone Routing • Given a placement of the blocks, we know the base pin locations (the columns of the base output pins, and the rows of the base input pins). • Only know one coordinate of the virtual pin (Y of virtual output pin and X of virtual input pin). • The trunks are assigned to the columns, and the branches are assigned to the rows. • Use "left-edge" algorithm to arrange trunks in columns and branches in rows. • Then we know the virtual pin positions (points). • Overflows in the "left-edge" packing are considered as routing violations. • The Fishbone scheme seeks a placement (and thus the routing) with no violation and some objective function (area and/or delay) minimized.

13. The Integrated Fishbone P&R • Simulated-annealing framework. • Sequence-pair • Base/virtual pin and Fishbone routing • After a random move (swapping of blocks in the sequence pair, or swapping two I/O ports). • Evaluate area (sequence-pair) • Fishbone routing • Evaluate routing violation, wire length or delay

14. virtual input pins extended region pseudo branch The I/O Ports virtual output pin

15. Experiment • Compare the areas, wire lengths and run times of: • Placement and routing with Fishbone. • Placement with RST and Warp Router routing. • Placement with HP and Warp Router routing. • HP placement, post wire length measurement with RST. • Fishbone placement, post wire length measurement with RST. • Fishbone placement, Warp Router routing with base pins. • Fishbone placement, Warp Router routing with virtual pins.

16. Experimental Results • On average, the Fishbone scheme resulted in a 14% area overhead and a 5% increase in wire length. • A price paid for 100% routability and predictability known during placement. • Fishbone placement with virtual pins specified (FB ro-v) is 100% routable using the Wrouter. Also it runs much faster (because there are no violations to be repaired). pl: placed. p-RST: post-placement RST estimation. ro: Wrouter. ro-b: Wrouter. Routing with Fishbone placemen but with base pins only. ro-v: Wrouter. Routing with Fishbone placement and virtual pins.

17. Experimental Results • The run time of the Fishbone scheme is the time taken only by the simulated annealing phase, which is on average 80% less than for RST placement; the RST and HP placements need extra time for routing.

18. Discussion • Fishbone cannot handle obstructions in the routing layers. • No 90o rotations of the blocks are allowed. • Only vertical spine (trunk vertical). • Need a pre-defined grid radix GR. • Extension to timing-driven version is straightforward. • Easy for coupling capacitance extraction.