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OSINIT

OSINIT. Set. in. terrupt. v. ectors:. . Time-slice. clo. c. k. SCHEDULER. . Soft. w. are. in. terrupt. OSSER. VICES. . Keyb. oard. in. terrupts. IOData. OSSER. VICES. Examine. stac. k. to. determine. requested. op. eration. Call. appropriate. routine.

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OSINIT

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  1. OSINIT Set in terrupt v ectors:  Time-slice clo c k SCHEDULER  Soft w are in terrupt OSSER VICES  Keyb oard in terrupts IOData . . . OSSER VICES Examine stac k to determine requested op eration. Call appropriate routine. SCHEDULER Sa v e program state. Select a runnable pro cess. Restore sa v ed con text of new pro cess. Push new v alues for PS and PC on stac k. Return from in terrupt. (a) OS initialization, services, and scheduler IOINIT Set pro cess status to Blo c k ed. Initialize memory buffer address p oin ter and coun ter. Call device driv er to initialize device and enable in terrupts in the device in terface. Return from subroutine. IOD A T A P oll devices to determine source of in terrupt. Call appropriate driv er. If END = 1, then set pro cess status to Runnable. Return from in terrupt. (b) I/O routines KBDINIT Enable in terrupts. Return from subroutine. KBDD A T A Chec k device status. If ready , then transfer c haracter. If c haracter = CR, then { set END = 1; Disable in terrupts } else set END = 0. Return from subroutine. (c) Keyboard driver Figure 4.10. A few operating system routines.

  2. Main program MO V R0,#0 STR R0,EOL Clear EOL flag. ADR R1,D A T AIN Load address of Register D A T AIN. contents of CONTROL register. LDRB R0,[R1,#3] Get ORR R0,R0,#4 Set bit KEN in register CONTR OL STRB R0,[R1,#3] to enable k eyb oard in terrupts. MO V R0,#&50 Enable IR Q in terrupts in pro cessor MSR CPSR,R0 and switc h to user mo de. . . . IR In terrupt-service routine Q READ STMFD R13!, { R0  R2,R14 irq } Sa v e R0, R1, and R14 irq on the stack. register ADR R1,DATAIN Load address of D A T AIN. LDRB R0,[R1] Get input character. LDR R2,PNTR Load pointer v alue. STRB R0,[R2],#1 Store character and increment pointer. STR R2,PNTR Up date p oin ter v alue in the memory . CMPB R0,#&0D Chec k if Carriage Return. LDMNEFD R13!, { R0  R2,R14 irq } If not, restore registers SUBNES PC,R14 irq,#4 and return. LDRB Otherwise get CONTROL register. R0,[R1,#3] AND R0,R0,#&FB Clear bit KEN STRB R0,[R1,#3] to disable k eyb oard in terrupts. MO V R0,#1 Set EOL flag. STR R0,EOL LDMFD R13!, { R0-R2,R14 } Restore registers SUBS PC,R14 irq,#4 and return. Figure 4.13. An ARM interrupt-service routine to read an input line from a keyboard based on Figure 4.9.

  3. Bus D7 P A7 D A T AIN D1 D0 P A0 SIN Input CA status PB7 D A T A OUT PB0 SOUT CB1 Handshak e control CB2 Sla v e- 1 Ready Master - Ready R / W A31 My-address Address decoder A2 RS1 A1 RS0 A0 Figure 4.33. Combined input/output interface circuit.

  4. D A T A OUT D7 D Q 7 7 Printer data D0 D Q 1 1 D0 D Q 0 0 SOUT Idle Handshak e control V alid Read Load status data R/ W Sla v e- ready Go A31 My-address T iming Address Logic decoder A1 A0 Clock My-address Respond Idle Go=1 Figure 4.35. A parallel point interface for the bus of Figure 4.25, with a state-diagram for the timing logic.

  5. Main Processor memory Processor b us Bridge PCI b us Additional SCSI Ethernet USB ISA memory controller interf ace controller interf ace SCSI b us IDE disk V ideo Disk CD-R OM controller controller CD- Disk 1 Disk 2 K e yboard Game R OM Figure 4.38. An example of a computer system using different interface standards.

  6. Host computer Root hub Hub Hub I/O I/O I/O I/O Hub de vice de vice de vice de vice I/O I/O de vice de vice Figure 4.43. Universal Serial Bus tree structure.

  7. Host computer Root Hub HS HS Hub A Hub B F/LS HS HS - High speed F/LS - Full/Lo w speed De vice De vice C D Figure 4.44. Split bus operation

  8. PID PID PID PID PID PID PID PID PID 0 1 2 3 0 0 1 2 3 (a) Packet identifier field Bits 8 7 4 5 PID ADDR ENDP CRC16 (b) Token packet, IN or OUT Bits 8 0 to 8192 16 PID D A T A CRC16 (c) Data packet Figure 4.45. USB packet format.

  9. Bits 8 11 5 PID Frame number CRC5 (a) SOF Packet 1-ms frame S T3 D T7 D S T3 D S - Start-of-frame pack et T n - T ok en pack et, address = n D - Data pack et A - A CK pack et (b) Frame example Figure 4.47. USB frames.

  10. Table 4.4 The SCSI bus signals. Category Name F unction – Data DB(0) to Data lines: Carry one b yte of information – DB(7) during the information transfer phase and iden tify device during arbitration, selection and reselection phases – DB(P) P arit y bit for the data bus – Phase BSY Busy: Asserted when the bus is not free – SEL Selection: Asserted during selection and reselection – Information C/D Con trol/Data: Asserted during transfer of t yp e con trol information (command, status or message) – MSG Message: indicates that the information b eing transferred is a message – Handshak e REQ Request: Asserted b y a target to request a data transfer cycle – A CK Ac kno wledge: Asserted b y the initiator when it has completed a data transfer op eration – Direction of I/O Input/Output: Asserted to indicate an input e transfer op eration (relativ to the initiator) – A Other TN A tten tion: Asserted b y an initiator when it wishes to send a message to a target – RST Reset: Causes all device con trols to disconnect from the bus and assume their start-up state

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