Download
1 / 27
270 likes | 551 Views
08/09 学年第 1 学期. 硬件描述语言及器件. 教材：任勇峰等编著 《VHDL 与硬件实现速成 》. 主讲教师：刘文怡. 教学安排. 第 1 讲： VHDL 概述及其开发环境 第 2 讲： VHDL 的基本元素 第 3 讲： VHDL 的进程 第 4 讲：其它并行语句 第 5 讲： VHDL 实例剖析 第 6 讲： VHDL 的顺序描述语句 第 7 讲：结构体的描述风格 第 8 讲：计数器状态控制 第 9 讲：不同风格的状态机设计 第 10 讲： VHDL 综合举例. 第 10 讲： VHDL 综合举例. 1 上节内容回顾
E N D
08/09学年第1学期 硬件描述语言及器件 教材：任勇峰等编著《VHDL与硬件实现速成》 主讲教师：刘文怡
教学安排 • 第1讲：VHDL概述及其开发环境 • 第2讲：VHDL的基本元素 • 第3讲：VHDL的进程 • 第4讲：其它并行语句 • 第5讲：VHDL实例剖析 • 第6讲：VHDL的顺序描述语句 • 第7讲：结构体的描述风格 • 第8讲：计数器状态控制 • 第9讲：不同风格的状态机设计 • 第10讲：VHDL综合举例
第10讲：VHDL综合举例 • 1 上节内容回顾 • 2 使用完整框架编写一个4路二输入异或门。 • 3 使用组件语句编写一个4位的移位寄存器。 • 4 具有通道选择的单输入8输出的通道选择器。 • 5 使用选择语句设计一个带使能的2－4译码器。 • 6 使用条件语句设计74ls688比较器 • 7 生成ADS8402的控制时序，实现数据采集。 • 8 按定义实现写时序
1 上节内容回顾 • 计数型结构 • 递变型对比 • 枚举类型定义状态机 • 带复位的状态机 • Moore状态机 • Mealy状态机
计数型结构 • PROCESS (clr，clk) • BEGIN • IF(clr=1) THEN • Count_B<=“00000000”; • q <= ‘0’; • ELSIF (clk'EVENT AND clk= ‘1’ ) THEN • IF (Count_B = “00001111”) THEN • Count_B<=“00000000”; • else • Count_B<=count_B + 1; • IF (Count_B = “00000000”) THEN • q <= ‘1’; • ELSIF (Count_B = “00000001”) THEN • q <= ‘0’; • ELSIF (Count_B = “00000011”) THEN • q <= ‘1’; • ELSIF (Count_B = “00000100”) THEN • q <= ‘0’; • END IF; • END IF; • END IF; • END PROCESS;
特点 • 随着CLK的推进，计数器独立运转，不受各状态的支配； • 计数器的每一计数值都可以用来对应不同的状态，这些状态都会遍历到，即使很多数值未出现，它也是存在的； • 计数值的顺序决定了各状态发生的次序，这一次序是确定的； • 计数的最大值决定了状态是有限的； • 不同状态间的时间间隔是确定的，精确的； • 具有明显的周期性。 CLK 计数器 状态变更
IF (Count_B = “00001111”) THEN • Count_B<=“00000000”; • else • Count_B<=count_B + 1; • IF (Count_B = “00000000”) THEN • q <= ‘1’; • ELSIF (Count_B = “00000001”) THEN • q <= ‘0’; • ELSIF (Count_B = “00000011”) THEN • q <= ‘1’; • ELSIF (Count_B = “00000100”) THEN • q <= ‘0’; • END IF; • END IF; 递变型对比 • IF (Count_B = “00000000”) THEN • Count_B <= “00000001”; q <= ‘1’; • ELSIF (Count_B = “00000001”) THEN • Count_B <= “00000010”; q <= ‘0’; • ELSIF (Count_B = “00000010”) THEN • Count_B <= “00000011”; -- ???? • ELSIF (Count_B = “00000011”) THEN • Count_B <= “00000100”; q <= ‘1’; • ELSIF (Count_B = “00000100”) THEN • Count_B <= ?????????; q <= ‘0’; • END IF;
结论 • 随着CLK的推进，“计数器”已失去计数的功能，仅是个标志而已，计数器的值也不具有实际大小方面的意义； • 计数器出现的每一计数值都可以用来对应不同的状态，但未出现的值是不存在的，没有状态与之对应； • 因计数值已不具数值意义，状态间发生的次序完全由递变关系决定，与数本身大小无关，次序也不确定； • 计数的最大值不代表存在这么多状态； • 不同状态间的时间间隔是不确定的； • 不具有周期性。
枚举类型定义状态机 • 定义方式：type 名称 is (元素1,元素2…); • 举例： • type week is (mon, tue, wed, thu, fri, sat, sun); • type std_logic is (‘U’,‘X’,'0‘,'1‘,‘Z’,‘W’,‘L’,‘H’,‘-’); • type states is (state0,state1,state2,state3);
带复位的状态机 ARCHITECTURE arc OF ss IS type states is (st0,st1,st2,st3); signal outc: states; BEGIN PROCESS(clk) BEGIN IF reset='1' then outc<=st0 ; elsif clk'event and clk='1' then CASE outcIS WHEN st0 => outc<= st1; WHEN st1 => outc<= st2; WHEN st2 => outc<= st3; WHEN st3 => outc<= st0; WHEN OTHERS => outc<="001"; ENDCASE; end if; END PROCESS; END arc;
Moore状态机 ARCHITECTURE a OF moore IS TYPE State IS (s0,s1,s2,s3); SIGNAL present_state : State; SIGNAL next_state: State; BEGIN state_comp: PROCESS(present_state) BEGIN CASE present_state IS WHEN s0 => IF X = '0' THEN next_state <= s0; ELSE next_state <= s1; END IF; OP <= '1'; WHEN s1 => IF X = '0' THEN next_state <= s3; ELSE next_state <= s2; END IF; OP <= '0'; WHEN s2 => IF X = '0' THEN next_state <= s2; ELSE next_state <= s3; END IF; OP <= '1'; WHEN s3 => IF X = '0' THEN next_state <= s3; ELSE next_state <= s0; END IF; OP <= '0'; END CASE; END PROCESS state_comp; PROCESS (CLK) BEGIN IF CLK'EVENT AND CLK = '1‘THEN present_state <= next_state; END IF; END PROCESS; END a;
Mealy状态机 ARCHITECTURE a OF mealy IS TYPE State IS (s0,s1,s2,s3); SIGNAL present_state : State; SIGNAL next_state: State; BEGIN state_comp: PROCESS(present_state) BEGIN CASE present_state IS WHEN s0 => IF X = '0' THEN next_state <= s0; ELSE next_state <= s1; END IF; IF X = '0' THEN op <= '0'; ELSE op <= '1'; END IF; WHEN s1 => IF X = '0' THEN next_state <= s3; ELSE next_state <= s2; END IF; IF X = '0' THEN op <= '1'; ELSE op <= '1'; END IF; WHEN s2 => IF X = '0' THEN next_state <= s2; ELSE next_state <= s3; END IF; IF X = '0' THEN op <= '0'; ELSE op <= '1'; END IF;
WHEN s1 => IF X = '0' THEN next_state <= s3; ELSE next_state <= s2; END IF; IF X = '0' THEN op <= '1'; ELSE op <= '1'; END IF; WHEN s2 => IF X = '0' THEN next_state <= s2; ELSE next_state <= s3; END IF; IF X = '0' THEN op <= '0'; ELSE op <= '1'; END IF; WHEN s3 => IF X = '0' THEN next_state <= s3; ELSE next_state <= s0; END IF; IF X = '0' THEN op <= '0'; ELSE op <= '0'; END IF; END CASE; END PROCESS state_comp; PROCESS (CLK) BEGIN IF CLK'EVENT AND CLK = '1' THEN present_state <= next_state; END IF; END PROCESS; END a;
2 使用完整框架编写一个4路二输入异或门 A(0) Q(0) B(0) A(1) Q(1) B(1) A(2) Q(2) B(2) A(3) Q(3) B(3)
4 具有通道选择的单输入8输出的通道选择器 a Q sel
5 使用选择语句设计带使能的2－4译码器 oen Q d
6 使用条件语句设计74ls688比较器 • 见课本
convst • rd • cs • reset • byte • db • busy
<630ns >650ns 采集时序 >40ns >20ns
设计思路 • 设采样率500ksps，则采样周期为2000ns，由于关键的几个计时段要求大于20ns、40ns、650ns，可以采用100ns的计时步长，故采用晶振频率为10MHz。计数器循环最大次数为20次，5位信号向量即可。 • 0 8 9 16 19 • 关键时间：0、800ns、900ns、1600ns、2000ns
PROCESS (rst，clk) • BEGIN • IF(rst=‘1’) THEN • Count_B<=“00000”; • q <= ‘0’; • ELSIF (clk'EVENT AND clk= ‘1’ ) THEN • IF (Count_B = “10011”) THEN • Count_B<=“00000”; • else • Count_B<=count_B + 1; • IF (Count_B = “00000”) THEN • CONVST <= ‘0’; • ELSIF (Count_B = “01000”) THEN • RD <= ‘0’; CONVST <= ‘1’; • ELSIF (Count_B = “01001”) THEN • dat <= DB; • ELSIF (Count_B = “10000”) THEN • RD <= ‘1’; • END IF; • END IF; • END IF; • END PROCESS;
其它控制语句 • CS <= ‘0’; • BYTESEL <= ‘0’; • RESET <= ‘1’; • PROCESS (rst，clk) • BEGIN • IF(rst=‘1’) THEN • Count_B<=“00000”; • q <= ‘0’; • ELSIF (clk'EVENT AND clk= ‘1’ ) THEN • .. .. .. .. .. • END IF; • END PROCESS;
8 按定义实现写时序 • 一旦探测到“写允许”WREN变低，FPGA控制8位数据线给出数据X，然后“写”信号WR有效（变低），等到“接收完成”ROK信号变低，控制“写信号”WR变高，等待下一次“写允许”，发送X+1……，如此循环，写入递增数据。
ARCHITECTURE arc OF ss IS • type states is (st0,st1,st2,st3); • signal outc: states; • Signal dat: std_logic_vector(7 downto 0); • BEGIN • PROCESS(clk) • BEGIN • IF reset='1' then • outc <=st0 ; • dat <= “00000000”; • elsif clk'event and clk='1' then • CASE outc IS • WHEN st0 => • if WREN=‘0’ then • dbus <= dat; • WR <= ‘0’; • outc <= st1; • else outc <= st0;
CASE outc IS • WHEN st0 => • if WREN=‘0’ then • dbus <= dat; • WR <= ‘0’; • outc <= st1; • else outc <= st0; • WHEN st1 => • if ROK=‘0’ then • WR <= ‘1’; • outc <= st2; • else outc <= st1; • WHEN st2 => • dat <= dat + 1; • outc <= st0; • WHEN OTHERS => outc <=st0; • ENDCASE; • end if; • END PROCESS; • END arc;
