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The integrated Development of Embedded linux and SOC IP

The integrated Development of Embedded linux and SOC IP. 吳奇峰 新華電腦股份有限公司 應用工程師. Topics. SOC 系統發展流程 FPGA 發展工具 SOPC Builder 流程. SOC 嵌入式系統開發流程. System Requirement. Design Specification. Components, IP Sourcing. H/W & S/W partitioning. H/W Design synthesis. S/W Design. IC Tool.

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The integrated Development of Embedded linux and SOC IP

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  1. The integrated Development of Embedded linux and SOC IP 吳奇峰 新華電腦股份有限公司 應用工程師

  2. Topics • SOC 系統發展流程 • FPGA 發展工具 • SOPC Builder 流程

  3. SOC 嵌入式系統開發流程 System Requirement Design Specification Components, IP Sourcing H/W & S/W partitioning H/W Design synthesis S/W Design IC Tool Compiler ICE CO-simulation Debugger OS H/W & S/W adoption trade-off by verification Product

  4. Creator Motherboard • Memory: 2M Bytes Flash Memory、16M Bytes SDRAM 、 EEPROM • Communication: UART、Ethernet、USB 1.1 、I2C • Human-Machine Interface: Codec 、CMOS Camera、Ｋeypad、LED、7-Seg、　DIP Switch、LCD • Master and Slave Bus for daughter board Changeable: Create S3C4510 (ARM7TDMI) Create ARM920T-S3C2410 Create ARM922T-EPXA1 (for SOPC) Create FPGA-EP1C6 Create FPGA-XC2S Create TIDSP-5502

  5. Create FPGA-EP1C6 • FPGA: EP1C6;BQ240(5980LEs) • Codec: Stereo out Microphone in • 8-Bit serial I/O ADC with 2-channel multiplexed • SRAM:128K*8-Bit • 7-Seg LED • 9 LED Lamps • 4-Way DIP Swich • 1 Tag Switch • 1 DC Buzzer for tone generation

  6. Create FPGA-EP1C6 • PS2 Connector • Build-in Altera ByteBlasterMV Parallel Port download cable header circuit • Extension connector 27 pins for memory interface 50 pins for user definable I/O One 8-Bit ADC input 4 Pins Codec I/O 5V DC output • Slave Bus Communicate with Master Bus site CPU Keypad Switch 、UART interface

  7. Create FPGA-EP1C6 BlockDiagram Config CKT SRAM PC DIP-SW ICE LED 7-Seg Cyclone EP1C6 FPGA PS2 Creator BUS (Slave Bus) Buzzer Clock A2D VR MIC STEREO CODEC Buffer Regulator Expansion I/O

  8. Create FPGA-XC2S • FPGA: XC2S,PQ208(200K gate counts) • Codec: 16-Bit, 26-KSPS,TLV320AIC12 Built-in Microphone • 8-Bit serial I/O ADC with 2-channel multiplexer • SRAM: 128K*8Bit • 7-Seg LED • 9 LED Lamps • 4-Way DIP Switch • 1 Tag Switch

  9. Create FPGA-XC2S • PS2 Connector • Build-in Xilinx download cable header circuit • Extension connector 27 pins for memory interface 10 pins for user definable I/O One 8-Bit ADC input One 16-Bit Codec Aux input 5V DC output • Slave Bus Communicate with Master Bus site CPU Keypad Switch UART interface

  10. Create FPGA-XC2S Block Diagram Config CKT SRAM PC DIP-SW ICE LED 7-Seg Spartan-II FPGA PS2 Creator BUS (Slave Bus) Buzzer Clock A2D VR MIC STEREO CODEC Buffer Regulator Expansion I/O

  11. Creator Bus Communication Master Bus (CPU) Slave Bus Address Bus UART Data Bus Key Pad S3C4510 (ARM7TDMI) ARM920T S3C2410 I/O ARM922T EPXA1 (for SOPC) Power IRQ DMA FPGA Config. Controls TI DSP 5502 Creator Mother Board

  12. Create ARM922T-EPXA1 • CPU:EPXA1F484C3 ARM922T Core 100K Gate Count FPGA • 10/100 Ethernet • Master Bus • Two Clock Sources • 8M-Byte Flash Memory • 32M-Byte SDRAM • 8 LED Lamps • 4-Way DIP switch • 1 Tag Switch

  13. Create ARM922T-EPXA1 • 4 extension connectors for wire wrap board or special hardware module Totally 118 I/O pins 3 Clock Output pins 2 Fast input pins 5V DC Output • Header for ARM ICE JTAG Connector • Header for Altera Byte Blaster MV download cable • RunningLinux,Linux open source codes provided

  14. Create ARM922T-EPXA1 Board Architecture EPXA1 Control ARM JTAG Extension I/O PLD JTAG EPXA1 PLD LED/DIP SW/TAG SW POWER EPXA1 ARM-Strip SDRAM Flash Ethernet Clocks Create ARM922T-EPXA1 Master Bus JH1 JH2 Creator Motherboard

  15. Excalibur ARM Configuration SDRAM Flash ROM SRAM SDRAM Controller Expansion Bus Interface (EBI) UART Interrupt Controller Watchdog Timer ARM922T Processor AHB1 Configuration Logic Master AHB 1-2 Bridge Configuration Register AHB2 Single--Port SRAM Phase-Locked Loop (PLL) Reset Module Timer Dual-Port SRAM PLD-to-StripeBridge Stripe-to-PLD Bridge AHB AHB Excalibur Hard Processor FPGA Logic ProgrammableLogic Slave Peripheral ProgrammableLogic Slave Peripheral Programmable Logic Master Peripheral Programmable Logic Module Programmable Logic Module IP External Devices AHB: AMBA™ High-Performance Bus

  16. IP Modules Peripheral Library Select & Configure Peripherals, IP Hardware Development Software Development • EDIF Netlist • HDL Source Files • Testbench • C Header files • Custom Library • Peripheral Drivers Connect Blocks Generate Synthesis &Fitter GNUPro Compiler IAR ARM Compiler uClinux/Linux • User Code • Libraries • OS(Kernel…….. • User Design • Other IP Blocks Quartus II Software Tools SOPC Builder Flow Intellectual Property Intellectual Property SOPC Builder GUI Custom Instructions Processor Library Configure Processor Executable Code Hardware Configuration File Verification & Debug JTAG Microtime Carrier ICE Domingo Debugger For uClinux/Linux CREAE ARM922T EXPA1

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