1 / 11

Project Kokanee: TTL 7400 Series Logic Tester using CMOS VLSI

Project Kokanee: TTL 7400 Series Logic Tester using CMOS VLSI. Team John McGlone Drew Willis *Paul Berardi * = Team Leader. Advisor Dr. Albright, Dr. Osterberg Industry Representative Mr. Steve Kassel Intel (Retired). Overview. Project Review High Level Functional Block Diagram

minna
Download Presentation

Project Kokanee: TTL 7400 Series Logic Tester using CMOS VLSI

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Project Kokanee: TTL 7400 Series Logic Tester using CMOS VLSI Team John McGlone Drew Willis *Paul Berardi * = Team Leader • Advisor • Dr. Albright, Dr. Osterberg • Industry Representative • Mr. Steve Kassel • Intel (Retired) University of Portland School of Engineering

  2. Overview • Project Review • High Level Functional Block Diagram • VLSI Chip Overview • VLSI – DUT interface • VLSI Layout • Prototype Board • Milestones • Accomplishments • Plans • Issues/Concerns University of Portland School of Engineering

  3. Functional Block Diagram University of Portland School of Engineering

  4. VLSI Chip Overview University of Portland School of Engineering

  5. VLSI Pin Electronics to DUT Pin Interface University of Portland School of Engineering

  6. VLSI Layout University of Portland School of Engineering

  7. Milestones University of Portland School of Engineering

  8. Accomplishments • Milestone 9 completed – PIC program completed • Milestone 10 completed –VLSI chip received, tested and debugged • Prototype in progress • 10 DUTs pass/fail vectors correctly so far • Updated website University of Portland School of Engineering

  9. Plans • Continue prototype • Finish verifying test vectors • Prototype Release • Founders Day Presentation • Final Report • Post Mortem • Continue updating website University of Portland School of Engineering

  10. Concerns/Issues • Conversion from test bed to prototype • Time management University of Portland School of Engineering

  11. Questions? University of Portland School of Engineering

More Related