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ECE 171 Digital Circuits Chapter 3 Data Encoding and Floating-Point Numbers

ECE 171 Digital Circuits Chapter 3 Data Encoding and Floating-Point Numbers. Herbert G. Mayer, PSU Status 4/22/2018 Copied with Permission from prof. Mark Faust @ PSU ECE. Syllabus. Floating Point Numbers IEEE 754 Standard Other Formats BCD ASCII Gray Code Error Correction, 4-bit

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ECE 171 Digital Circuits Chapter 3 Data Encoding and Floating-Point Numbers

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  1. ECE 171Digital Circuits Chapter 3Data Encoding and Floating-Point Numbers Herbert G. Mayer, PSU Status 4/22/2018 Copied with Permission from prof. Mark Faust @ PSU ECE

  2. Syllabus Floating Point Numbers IEEE 754 Standard Other Formats BCD ASCII Gray Code Error Correction, 4-bit Error Correction, 8-bit

  3. Sign Mantissa Exponent Floating Point • Represent real AKA floating point numbers • “God invented integers, man created floating point numbers”  • Fixed point too restrictive for precision and range; is typical on IBM/370 and later! • Similar to common scientific notation + 6.022 x 1023 Normalized mantissa: single digit to left of decimal point

  4. Sign Exponent IEEE 754 Floating Point Standard Sign Binary Exponent Significand + 1.101011 x 212 Mantissa 1 Fraction Normalized binary mantissa will always have leading 1 so we can assume it. Get 1 extra bit of precision instead Exponents are stored with a bias, added to the exponent before being stored Allows fast magnitude compare Used on virtually all computers Several levels of precision/range: Single, Double, Double-Extended

  5. IEEE 754 Floating Point Standard • Single Precision, 32 bits, 8-bit exponent • Bias = 127, scales exponent by adding 127 • Value 255 is excluded! Special need! 1 8 23 ± Exponent + Bias Significand 0 31 30 23 22 F = -1Sign x (1+Significand) x 2Exponent - Bias

  6. IEEE 754 Floating Point Standard F = -1Sign x (1+Significand) x 2(Exponent-Bias) Example: 1 8 23 1 10000001 01000000000000000000000 0 31 30 23 22 - 129 = 0.2510 = - 1.012 x 2(129-127) = - 1.25 x 2(129-127) = - 1.25 x 22 = - 1.25 x 4 = - 5.0

  7. IEEE 754 Floating Point Standard • Will commonly see these expressed as hex 1 8 23 1 10000001 01000000000000000000000 0 31 30 23 22 C0A00000

  8. IEEE 754 Floating Point Standard • Some Special Cases • Zero (no assumed leading 1) • Exponent = 0, Significand = 0 • NaN (Not a Number), e.g. ¥ • Exponent = 255 • Denormalized numbers • Now known as: subnormal! • Exponent = 0, Significand ¹ 0

  9. Gaps! b a - + 0 IEEE 754 Floating Point Standard • Why do we need subnormal numbers? • Addresses gap caused by implicit leading 1 • Smallest positive number (a) is 1.000…000 x 2-126 • Next number (b) is 1.000…001 x 2-126 =(2-126 + 2-149) S Exponent Significand 1 8 23 = 0 = 1.00000000000000000000001 x 2-127 = 1.00000000000000000000010 x 2-127 = 1.00000000000000000000011 x 2-127 = 1.00000000000000000000100 x 2-127 0 00000000 00000000000000000000000 0 00000000 00000000000000000000001 0 00000000 00000000000000000000010 0 00000000 00000000000000000000011 0 00000000 00000000000000000000100 Distance from zero to smallest positive number is 1.00000000000000000000001 x 2-127 ~= 2-127 Distance to next number is 0.00000000000000000000001 x 2-127 = 2-23 x 2-127 = 2-150

  10. IEEE 754 Floating Point Standard • Subnormal Numbers • Solution – Non-normalized form • Exponent = 0, Significand != 0 • Implicit Exponent of -126 • F = -1Sign x (Significand) x 2(-126) • Smallest positive number (a) = 0.000…001 x 2-126 = 2-149 • Next smallest number (b) = 0.000…010 x 2-126 = 2-148

  11. Other IEEE 754 Formats Half precision (binary16) Single precision (binary32) Double precision (binary64) Quadruple precision (binary128)

  12. Other Float Formats X86 Extended precision (80 bits)

  13. BCD (Binary Coded Decimal) • Used in early 4-bit mP • Early IBM 360 family to support Cobol • Simple displays • 4 Bits/Decimal Digit

  14. ASCII • American Standard Code for Information Interchange (pronounced: As’ key) • For encoding text • Universally used. Other standard codes: • EBCDIC (old IBM mainframe standard) died out • Unicode for international (non-Romance, like Chinese) languages, needing more than 8 bits • About 60,000 Chinese characters can be represented with 2 bytes = 64k or 65,536 symbols

  15. “ECE171” 1000101100001110001010110001011011101100010000000 As a C string

  16. Reflective Gray Code (RGC) • Adjacent codes differ by single bit • “Unit Distance Code” • Often used in interfacing mechanical sensors

  17. Reflective Gray Code

  18. 7-Segment Code

  19. Serial Data Transmission & Storage • Parallel • Storage: each bit of word read/written simultaneously • Transmission: each bit has separate signal path • Serial • Reduce costs • Simplify design • Higher speed (LVDS, skew) • Applications • USB • PCI Express

  20. Serial Data Transmission & Storage • Clock • Determines rate at which bits are transmitted (“bit rate”) • “bit time”= clock period (1/bit rate) = “bit cell” • Sync • Determines start of byte (or packet) • Data Format • Determined by “line code”

  21. Serial Data Transmission & Storage • NRZ – Non Return to Zero • NRZI – Non Return to Zero Invert (on ones) • Transition based • Differential signaling: USB • RZ – Return to Zero • BPRZ – Bipolar Return to Zero • “DC balanced” • MLT-3 (100 Base T Ethernet) • Manchester encoding • Guarantees a transition in every bit cell • Facilitates clock recovery • Requires higher bandwidth • Original coax-based 10 Mbps Ethernet • Other techniques for DC balancing (and edge density) • m-out-of-n-codes (e.g. 8B10B): Gigbabit Ethernet

  22. + Device A Device B Device A Device B - + - Why Serial? “Parallel” “Serial” 10 bidirectional wires at 250Mbps pair unidirectional wires at 2500Mbps (2.5Gbps)

  23. Traditional Parallel Bus Device A Device B • Used in low to medium 100 MHz range • Issues • Board trace length effect on skew • Clock skew across devices • Faster data rate squeezes “eye”

  24. Source Synchronous Bus (SSB) • SSB is a fast technique used for timing information on limited digital interface • Overcome limits of transmission > 250 MHz and > 5 inches line length on PC-board • Transmitting device sends a clock signal along with the data signals • The clock is then initiated on the receiving side • Goal to avoid skew error • Drawback of source synchronous clock is creation of separate clock-domain on the receiving device

  25. Source Synchronous Bus Device A Device B • Used in ~250 MHz to 1.6 GHz range • Clock signal is “forwarded” with data • Design impact: • Board layout track length mismatch still adds to skew • Eliminates skew error term caused by clock domain skew • Allows faster cycle times than traditional parallel bus

  26. Embedded Clock Data Clock Clock signal embedded with data • Clock signal is “embedded” with data • Received used digital phase locked loop (DPLL) to “recover” clock and determine where bit times are • Edge density to be guaranteed by encoding scheme • Examples • PCI Express, USB, Serial RapidIO, Infiniband • Intel’s new QuickPath Interconnect

  27. Device A Device B Device B “locks” onto edgesto be in sync with pulse stream Edge Lock Technique (Tracking Receiver) Device A sends pulse train to Device B

  28. 8B/10BDecoder Deserializer RX FIFO Ensure Edge Density: m-of-n codes Device A Device B + _ ParallelData 8B/10BEncoder Serializer ParallelData TX FIFO 8B/10BDecoder RX FIFO Deserializer • Some 8-bit code words have too few 1s (or 0s) to ensure edge density sufficient to recover clock • 8b10 encoding (developed by IBM in 1983) • Use 10-bit code words, but only use a subset of the available 210 code words • No more than five 0s or 1s in a row • Balanced number of 0s and 1s (difference between count of 0s and 1s in a string of at least 20 bits is no more than two. • Benefits • Ensure edge density • Avoid DC bias at receiver from imbalance • Running disparity for unbalanced codewords • 256 data characters • All 8-bit bytes • 12 control characters (INIT, etc) ParallelData + _ ParallelData Serializer 8B/10BEncoder TX FIFO 8 bit byte 10 bit code Table lookup

  29. Error Detection and Correction • During data transmission, numerous causes for errors can occur • Adding redundancy, allows certain types of errors to be detected • Or even corrected • We discuss single-bit error detection and correction using checksums • Techniques promoted by: • ANSI American national Standard Institute • TIA Telecommunication Industry of America • EIA Electronics Industry Alliance

  30. Error Detection and Correction • Errors occur during data storage/retrieval and transmission • Noise, cross-talk, EMI, cosmic rays, impurities in IC materials • More common with higher speeds and lower voltages • Use m-out-of-n codes to detect errors • Not all possible codes are used (valid) • Errors in used (valid) codes (hopefully) produce unused (invalid) codes • Example: Luhn Algorithm • Credit cards, IMEI (International Mobile Equipment Identity) • Start from right, double every second digit • Add all digits • Add a final check digit to ensure sum is multiple of 10

  31. Error Detection and Correction • Restricting the detection to single-bit errors • For multi-bit error detection and correction: Add further redundancy • Design issue, whether to include check sums in error correction procedure • Will require more bits • At the core of error detection and correction: Redundancy

  32. Error Correction, 4-bit data • Use 4-bit data, 8 instances, per check • View data stream as sequence of 8 rows of 4-bit data • Each of 8 rows receives checksum bit for 4 data bits. Adding a columns for the 5th bit • Each of the 4 columns of 8 rows receives a checksum bit, adding a new row for 9th bit • “1” bits are counted; if the number is odd, add a “1” checksum bit, else “0” check bit • Works analogously by counting “0” bits

  33. Error Correction, 4-bit data Good data, correct checksums: data yellow

  34. Error Correction, 4-bit data Single-bit error occurred. Where is it?

  35. Error Correction, 4-bit data Single-bit error corrected!

  36. Error Detection, 8-bit data Transmission of 8-bit data, 8 instances = rows

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