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嵌入式微處理器系統

嵌入式微處理器系統. Professor: Mon-Chau Shie 2010/04/09. Topic. 1. RISC 32 bit CPU Architecture Introduction. Outline. 1.1 ARM vs. MIPS MIPS Overview ARM Overview 1.2 S3C4510 (ARM7) Overview Samsung S3C4510B 1.3 IXP (XScale) Overview. MIPS Overview .

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嵌入式微處理器系統

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  1. 嵌入式微處理器系統 Professor: Mon-Chau Shie 2010/04/09

  2. Topic. 1 RISC 32 bit CPU Architecture Introduction

  3. Outline 1.1 ARM vs. MIPS • MIPS Overview • ARM Overview 1.2 S3C4510 (ARM7) Overview • Samsung S3C4510B 1.3 IXP (XScale) Overview

  4. MIPS Overview • The MIPS (Million Instruction Per Second) architecture grew out of research started at Stanford University (Professor John Hennessy). • MIPS project was one of the first publicly known implementations of a Reduced Instruction Set Computer (RISC) architecture. • MIPS processor implemented a smaller, simpler instruction set. • MIPS processor used a technique called pipelining to more efficiently process instructions. • MIPS used 32 registers, each 32 bits wide.

  5. MIPS Instruction Set Overview • MIPS instruction set consists of about 111 total instructions, each represented in 32 bits. • An example of a MIPS instruction is below: • add $r10, $r7, $r8 000000 00111 01000 01010 00000 010100 $r10 $r7 $r8

  6. MIPS Overview • For detail information about the “MIPS Architecture”, you can refer to [5]

  7. Outline 1.1 ARM vs. MIPS • MIPS Overview • ARM Overview 1.2 S3C4510 (ARM7) Overview • Samsung S3C4510B 1.3 IXP (XScale) Overview

  8. ARM Overview • Advances RISC Machines (now known as ARM) was established in November 1990. • ARM (formerly Advanced RISC Machines) • ARM7, ARM9, ARM10, ARM 11 • StrongARM, Xscale (PXA, IXP, IXC, etc.) • The standard way to perform I/O functions on ARM systems is by the use of memory- mapped I/O.

  9. ARM Overview • ARM is fully 16/32-bit RISC architecture • ARM variants are in widespread use in embedded and Low-power applications due to their power saving design features. • Power consumption: CPU Power W Clock /MHz • ARM7TDMI: < 0.25 60 -110 • ARM7TDMI-S: < 0.4 >50 • ARM9TDMI: 0.3 167 - 220 • ARM1020E: ~0.85 200 - 400 • IXP (XScale): 1.2 533 • Inter 486 cpu: 10 50

  10. ARM Overview • ARM incorporates the following typical RISC architecture features: • A load/store architecture • data-processing operations only operate on register contents, not directly on memory contents. • Simple addressing modes • all load/store addresses being determined from register contents and instruction fields only. • Pipelined • (ARM7: 3 stages) • (ARM7: 5 stages) • Uniform and fixed-length instruction fields, to simplify instruction decode.

  11. ARM Overview • The ARM processor has a total of 37 registers: • 31 general-purpose 32bit registers. • 6 status registers. • 16 general registers and one or two status registers are visible at any time. • The visible registers depend on the processor mode. • The other registers (the banked registers) are switched in to support IRQ, FIQ, Supervisor, Abort and Undefined mode processing.

  12. ARM Overview • Registers: • R0 to R15 are directly accessible. • R0 to R12 are general purpose. • R13 is the Stack Pointer (SP). • R14 is the Link Register (LR). • R15 is the Program Counter (PC).

  13. ARM Overview • Current program status register (CPSR) • CPSR is accessible in all processor modes. • It contains the following condition code: • Flags, interrupt disable bits, the current processor mode, other status and control information. • Saved program status register (SPSR) • SPSR is used to preserve the value of the CPSR when the associated exception occurs.

  14. ARM Overview • Register organization in ARM state • Registers are arranged in partially overlapping banks, with a different register bank for each processor mode, as shown in Figure 1. Figure.1 Ref. [2]

  15. ARM Overview • For detail information about the ARM CPU Architecture and Register organization, we will introduce in Chap 3.

  16. ARM vs. MIPS

  17. Outline 1.1 ARM vs. MIPS • MIPS Overview • ARM Overview 1.2 S3C4510 (ARM7) Overview • Samsung S3C4510B 1.3 IXP (XScale) Overview

  18. Samsung S3C4510B • Samsung S3C4510B • Samsung S3C4510B 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller solution for ethernet-based systems. • The S3C4510B is built around an outstanding CPU core: the 16/32-bit ARM7TDMI RISCprocessor designed by Advanced RISC Machines, Ltd.

  19. S3C4510B - Block Diagram S3C4510B CPU core Ref. [2]

  20. ARM7TDMI Overview • ARM7TDMI • T: THUMB • THUMB instruction set: 16 bit re-encoded subset of 32 bit ARM instruction set. • D: On-chip debug • Halt in response. • M: Long Multiply Instruction (‘M’ variant) • 32 bits x 32 bits = 64 bits. • Provide full 64 bit result. • I: Embedded ICE • On-chip breakpoint.

  21. ARM7TDMI Overview • Feature of ARM7TDMI Architecture: • 32 bit RISC processor (32-bit data & address bus) • Big and Little Endian operation modes • Fast interrupt response (for real-time applications) • Excellent high-level language support • Simple but powerful instruction set

  22. ARM7TDMI Overview • From the programmer’s point of view, the ARM7TDMI can be in one of two states: • ARM state which executes 32-bit, word- aligned ARM instructions. • THUMB state which operates with 16-bit, half- word-aligned THUMB instructions. In this state, the PC uses bit 1 to select between alternate half-words.

  23. ARM7TDMI Overview • 3 stage pipeline: • The ARM7TDMI core uses a pipeline to increase the speed of the flow of instructions to the processor. Ref. [2]

  24. ARM7TDMI Overview • 3 stage pipeline: Ref. [2]

  25. Feature of S3C4510B Architecture • Important peripheral functions include • 8 Kbytes Unified Cache • The S3C4510B CPU has a unified internal 8K byte instruction/data cache. • Using cache control register settings, you can use part or all of this cache as internal SRAM. • To raise the cache hit ratio, the cache is configured using two-way set associative addressing. • The replacement algorithm is pseudo-LRU (Least Recently Used). • The cache line size is four words (16 bytes). When a miss occurs, four words must be fetched consecutively from external memory.

  26. Feature of S3C4510B Architecture • 8/16/32-bit External Bus Support • IIC Serial Interface • 10/100 Mbps Ethernet Controllerwith Dedicated DMA • The S3C4510B has an ethernet controller which operates at either 100-Mbits or 10-Mbits per second in half-duplex or full-duplex mode. • In half-duplex mode, the controller supports the IEEE 802.3 carrier sense multiple access with collision detection (CSMA/CD) protocol. • In full-duplex mode, it supports the IEEE 802.3 MAC control layer, including the pause operation for flow control.

  27. Feature of S3C4510B Architecture • 2 HDLCs with Dedicated DMA • 2 General-Purpose DMAs • The S3C4510B has a two-channel general DMA controller, called the GDMA. • The two-channel GDMA performs the following data transfers without CPU intervention: • Memory-to-memory (memory to/from memory) • UART-to-memory (serial port to/from memory) • 2 UARTs • Two 32-bit Programmable Timers

  28. Feature of S3C4510B Architecture • toggle mode and interval mode • 18 Programmable I/O Ports • Memory Controller with Refresh Control • PLL for System Clock • Package Type : 208 QFP • Operating at 3.3V ±10% • 5-V-tolerant I/O, 3.3-V output levels • Operating Frequency : Up to 50MHz

  29. System Manager • The S3C4510B microcontroller's system manager has the following functions: • To arbitrate system bus access requests from several master blocks, based on fixed priorities. • To provide the required memory control signals for external memory accesses. • To provide the required signals for bus traffic between the S3C4510B and ROM/SRAM and the external I/O banks. • To compensate for differences in bus width for data flowing between the external memory bus and the internal data bus. • S3C4510B supports both little and big endian for external memory or I/O devices.

  30. S3C4510B System Memory Map • To control external memory operations, the System Manager uses a dedicated set of special registers • The System Manager uses special register settings to control the generation and processing of the control signals, addresses, and data that are required by external devices in a standard system configuration. • Special registers are also used to control access to ROM/SRAM/Flash banks, up to four DRAM banks and four external I/O banks, and a special register mapping area. • The address resolution for each memory bank base pointer is 64K-bytes (16 bits). The base address pointer is 10bits. This gives a total addressable memory bank space of 16 M words.

  31. Samsung S3C4510B • The following integrated on-chip functions are described in detail in [2] — 8K-byte unified cache/SRAM — I2C interface — Ethernet controller — HDLC — GDMA — UART — Timers — Programmable I/O ports — Interrupt controller

  32. Outline 1.1 ARM vs. MIPS • MIPS Overview • ARM Overview 1.2 S3C4510 (ARM7) Overview • Samsung S3C4510B 1.3 IXP (XScale) Overview

  33. IXP (XScale) Overview • Intel XScale core • Intel StrongARM V5 compliant • 266, 400, and 533 MHz • 3 Network Processor Engines (NPE) • Ethernet filtering • ATM SARing • HDLC

  34. IXP (XScale) Overview (con’t) • USB 1.1 device controller • Full-speed • 16 endpoints • PCI controller • 32-bit interface • PCI Spec. Rev. 1.1 compatible • Host/option capable • Master/target capable • Two DMA channels • 264 MBps peak data rate

  35. IXP (XScale) Overview (con’t) • 2 Ethernet MACs • ADSL support • Hardware security accelerator • DES, 3DES, SHA-1, and MD5 • AES 128-bit and 256-bit • For VPN, Wireless,... Etc. applications • UTOPIA-2 Interface • Low Power consumption • 1.2W @ 533MHz

  36. IXP (XScale) Overview (con’t) • DSP support for: • TI DSPs supporting HPI-8/HPI-16 bus cycles • Internal bus monitoring unit • Seven 27-bit event counters • Monitors internal bus occurrence and duration events • High-speed UART • Expansion bus interface

  37. IXP (XScale) Overview (con’t) • Typical Applications • High performance DSL modem • High performance cable modem • Residential gateway • SME router • Integrated access device (IAD) • Set-top box • DSLAM • Access Points 801.11 a/b/g • Network Printers

  38. IXP (XScale) Architecture • IXP425 hardware block diagram

  39. IXP (XScale) Architecture • XScale core block diagram

  40. IXP (XScale) Core • Intel StrongARM V5TE compliant • Seven/eight-stage super-pipeline • Integer pipe • Multiply-accumulate (MAC) pipe • Memory pipe • Multiple-accumulate coprocessor • Can do 2 simultaneous, 16 bit, SIMD multiplies with 40-bit accumulation

  41. IXP (XScale) Core (cont’d) • Management unit • 32-entry, data memory management unit • 32-entry, instruction memory management unit • 32-KByte, 32-way, set associative instruction cache • 32-KByte, 32-way, set associative data cache • 2-KByte, 2-way, set associative mini-data cache • 128-entry, Branch Target Buffer • 8-entry write buffer • 4-entry fill and pend buffers • allow “hit-under-miss” operation with data caches • Debug unit • JTAG interface

  42. IXP (XScale) NPE • Network Processor Engine • Dedicated-function • High performance, hardware-multi-threaded • Dedicated instruction/data memory bus • Used to off load networking functions • Additional assist hardware • Hardware security accelerator • CRC, AAL 2, AES, DES, SHA-1, and MD5

  43. IXP425 Processing Power

  44. Reference [1] http://en.wikipedia.org/wiki/ARM_architecture [2] http://www.samsung.com/Products/Semiconductor/ SystemLSI/Networks/PersonalNTASSP/Communication Processor/S3C4510B/um_s3c4510b_rev1.pdf [3] ARM DUI 0021A “Programming Techniques“, 1995 [4] www.arm.com [5] http://cse.stanford.edu/class/sophomorecollege/ projects00/risc/mips/index.html

  45. Exercise • Please describe RISC properties. • What is pipeline? • Please describe ARM 4510 feature. • What is the Branch Target Buffer (BTB) of XScale core? • What major function does IXP425 target for? How does IXP425 support it? • What is the NPE of IXP4xx processor?

  46. Topic. 2 Embedded Linux Concept

  47. Outline 2.1 Linux Overview • Unix/Linux History • Linux Concept • Linux Command 2.2 Embedded Linux Overview • ARM Linux • uClinux • Embedded Linux Concept

  48. Unix/Linux History • 1985: The “GNU manifesto” is published in the March 1985 issue of Dr. Dobb's Journal. • 1989: SCO ships SCO UNIX System V/386, the first volume commercial product licensed by AT&T to use the UNIX System trademark • 1991 : Linus Torvalds develops Linux as an open source Unix clone • 1994 : Linux 1.0 is released. • 1995: SCO acquires UNIX Systems source technology business from Novell Corporation (which had acquired it from AT&T's UNIX System Laboratories). SCO also acquires UnixWare 2 operating system from Novell

  49. Unix/Linux History • 1996: Real-time Linux designated the RTLinux project released in 1996 by Michael Barabanov under Victor Yodaiken's supervision • 1997: Caldera ships OpenLinux Standard 1.1 May 5, 1997, the second offering in Caldera's OpenLinux product line • 2003: Linux Kernel Archive http://www.kernel.org/. The current full-featured version is 2.6 (released December 2003) and development continues • 2005: The latest stable version of the Linux kernel is 2.6.12.4 (released 2005-08)

  50. Outline 2.1 Linux Overview • Unix/Linux History • Linux Concept • Linux Command 2.2 Embedded Linux Overview • ARM Linux • uClinux • Embedded Linux Concept

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