1 / 17

Concurrent Test Generation

Vishwani D. Agrawal Alok S. Doshi. Concurrent Test Generation. Auburn University, Department of Electrical and Computer Engineering Auburn, AL 36849, USA. Problem Statement. To find the smallest test set to detect all single stuck-at faults in a combinational circuit. An existing solution:

mirit
Download Presentation

Concurrent Test Generation

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Vishwani D. Agrawal Alok S. Doshi Concurrent Test Generation Auburn University, Department of Electrical and Computer Engineering Auburn, AL 36849, USA ATS05: Agrawal and Doshi

  2. Problem Statement • To find the smallest test set to detect all single stuck-at faults in a combinational circuit. • An existing solution: • Group faults into fault sets using fault independence • Generate concurrent tests for each group • Contribution of this paper: Devise a simulation-based implementation for this solution. ATS05: Agrawal and Doshi

  3. Outline • Introduction • Simulation-based Independence Fault Collapsing • Simulation-based Concurrent Test Generation • Results • Conclusions ATS05: Agrawal and Doshi

  4. Introduction Problem of finding a minimal test: • Static compaction cannot guarantee optimality. • Dynamic compaction is complex. • Solution: Target both faults F1 and F2 at the same time to find a single test. We define this as concurrent test generation. . . . T(F2) T(F1) Test set for fault F2 Test set for fault F1 v2 v1 v3 ATS05: Agrawal and Doshi

  5. Fault Classification T(F1) T(F1) = T(F2) T(F2) F1 and F2 are equivalent. F1 dominates F2. T(F1) T(F2) T(F1) T(F2) F1 and F2 are independent. F1 and F2 are concurrently testable. ATS05: Agrawal and Doshi

  6. Example Circuit 2 4 a x 1 5 b 3 7 11 c y d 6 10 9 All faults are Stuck-at-1 type e 8 C17 - ISCAS85 Benchmark Circuit 1 R. K. K. R. Sandireddy and V. D. Agrawal, “Diagnostic and Detection Fault Collapsing for Multiple Output Circuits,” Proc. Design, Automation and Test in Europe (DATE) Conf., Mar. 2005, pp. 1014 - 1019. ATS05: Agrawal and Doshi

  7. Independence Matrix and Graph C17 - ISCAS85 Benchmark Circuit ATS05: Agrawal and Doshi

  8. Independence Fault Collapsing A “similarity” based algorithm [2] collapses the independence graph: 5,11,7 1,8 3,9,2 4,6,10 C17 - ISCAS85 Benchmark Circuit 2 A. S. Doshi and V. D. Agrawal, “Independence Fault Collapsing,” Proc. 9th VLSI Design and Test Symp., Aug. 2005, pp. 357 - 364. ATS05: Agrawal and Doshi

  9. Simulation-based Independence Fault Collapsing • The independence graph generation procedure [2] requires ATPG. • Here we present a new method for graph generation using simulation: • Start with a fully-connected independence graph for an equivalence collapsed fault set. • Simulation of random vectors without fault dropping removes edges between faults detected by the same vector. 2 A. S. Doshi and V. D. Agrawal, “Independence Fault Collapsing,” Proc. 9th VLSI Design and Test Symp., Aug. 2005, pp. 357 - 364. ATS05: Agrawal and Doshi

  10. Simulation-based Independence Fault Collapsing 301 74181 4-bit ALU ATS05: Agrawal and Doshi

  11. Simulation-based Concurrent Test Generation • For each group, generate all test vectors for the first fault in the group. • If the number of test vectors for a fault is large, use a subset (e.g., 250 maximum) of vectors. • Simulate all faults in the group to select one vector that detects most faults in that group. • If more vectors than one detect the same number of faults within the group, then select the vector that detects most faults outside the group as well. ATS05: Agrawal and Doshi

  12. 74181 4-bit ALU Result ATS05: Agrawal and Doshi

  13. Results * Sun Ultra 5 *** Pentium Pro PC ** Hamzaoglu and Patel, IEEE-TCAD, 2000 ATS05: Agrawal and Doshi

  14. Number of Vectors for Increasing Circuit Sizes (100% Stuck-at Coverage) Single-fault ATPG (no compaction) Concurrent ATPG Minimum achieved! (dynamic compaction) ATS05: Agrawal and Doshi

  15. CPU Seconds for Increasing Circuit Sizes (100% Stuck-at Fault Coverage) Concurrent ATPG Minimum achieved! (dynamic compaction) ATS05: Agrawal and Doshi

  16. Conclusion • Concurrent test generation produces compact tests when combined with independence fault collapsing. • ATPG and set covering problems have exponential time complexities. Hence, we cannot expect absolute optimality for large circuits. • The concurrent ATPG procedure of this paper gives significantly smaller, and sometimes the optimum, test sets. • There is scope for improving the simulation-based algorithms for independence fault collapsing and concurrent test generation. ATS05: Agrawal and Doshi

  17. Thank You! ATS05: Agrawal and Doshi

More Related