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Digital Design

Digital Design. Jeff Kautzer Univ Wis Milw. Review of Medium Scale Integration (MSI) Logic Circuits. Common digital system tasks are commercially available as MSI logic devices in many different TTL and CMOS families

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Digital Design

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  1. Digital Design Jeff Kautzer Univ Wis Milw

  2. Review of Medium Scale Integration (MSI) Logic Circuits • Common digital system tasks are commercially available as MSI logic devices in many different TTL and CMOS families • Functions such as decoding/encoding, multiplexing, demultiplexing, comparison, arithmetic, code converting, and data busing

  3. De-Multiplexers A Demultiplexer (DEMUX) takes a single input & distributes it over several outputs.

  4. 1-line-to-8-line demux

  5. 74138 style decoder can function as a demultiplexer with E1 used as the data input. Typical waveforms shown for a select code of A2 A1 A0 = 000 show that O0 is identical to the data input I on E1.

  6. Security monitoring system MUX/DEMUX Application

  7. Synchronous data transmission system

  8. One 16 bit transmission cycle

  9. Comparators A Comparator takes two inputs numbers and yields a result to indicate <, =, > 74HC85 4-bit magnitude comparator

  10. 74HC85 wired as a single 4-bit comparator Two 74HC85s cascaded to perform an 8-bit comparison

  11. Set Point Magnitude comparator used in a simple controller application

  12. Code Converters A code converter changes data presented in one type of binary code to another type of binary code Basic idea of a two-digit BCD(hex)-to-binary converter.

  13. BCD-to-binary Conversion • Compute the binary sum of the binary equivalents of all bits in the BCD representation that are 1s. Example 01010010(BCD) = 0000010 (2) + 001010 (10) + 0101000 (40) = 0110100 (52)

  14. BCD-to-binary converter with 74HC83 4-bit parallel adders.

  15. Data Bus Interface These circuits include tristate-able buffers and latches Time Division Multiplexing 3 different devices can transmit 8-bit data over an 8-line data bus to a µ-processor; only one device at a time is enabled so that bus contention is avoided.

  16. Truth table and logic diagram for the 74ALS173 tristate register

  17. Tristate registers connected to a data bus.

  18. Signal activity during the transfer of the data 1011 from register A to register C

  19. Simplified way to show signal activity on data bus lines.

  20. Simplified representation of bus arrangement.

  21. Bundle method for simplified representation of data bus connections. The “/8” denotes an 8 bit data bus.

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