Introduction to CMOS

1. EE2174Digital Logic and Lab Dr. Shiyan Hu Office: EERC 518 shiyan@mtu.edu Introduction to CMOS Adapted and modified from Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic.

2. Goal of this chapter • Present intuitive understanding on CMOS • Device • Interconnect • Inverter • Combinational Gate

3. Device

4. MOS Transistor Types and Symbols D G S NMOS D G S PMOS

5. Circuit Under Design

6. Circuit on the Chip A transistor

7. The MOS (Metal-Oxide-Semiconductor) Transistor Polysilicon Aluminum

8. |V | GS A Switch! An MOS Transistor Simple View of A Transistor

9. Silicon Basics • Transistors are built on a silicon substrate • Silicon forms crystal lattice with bonds to four neighbors

10. Doped Silicon • Silicon is a semiconductor • Pure silicon has no free carriers and conducts poorly • Adding dopants increases the conductivity • extra electrons (doped Borons) – n-type • missing electrons (doped Arsenic/Phosphorus) more holes) – p-type n-type p-type

11. NMOS Transistor Diffusion

12. NMOS - II • Refer to gate, source, drain and bulk voltages as Vg,Vs,Vd,Vb, respectively. • Vab=Va-Vb • Device is symmetric. Drain and source are distinguished electrically, i.e., Vd>Vs. • P regions have acceptor (Boron) impurities, i.e., many holes. • N regions have donor (Arsenic/Phosphorus) impurities, i.e., many electrons. • N+ and P+ are heavily doped N and P regions, respectively.

13. NMOS - III • Gate oxide are insulators, usually, silicon dioxide. • Gate voltage modulates current between drain and source, how?

14. Enhancement NMOS

15. Enhancement NMOS - II • Does not conduct when Vgs=0, except that there is leakage current. • When Vgs is sufficiently large, electrons are induced in the channel, i.e., the device conducts. This Vgs is called threshold voltage.

16. Enhancement NMOS III Positively Charged Negatively Charged

17. Enhancement NMOS - IV • When Vgs is large enough, the upper part of the channel changes to N-type due to enhancement of electrons in it. This is referred to as inversion, and the channel is called n-channel. • The voltage at which inversion occurs is called the Threshold Voltage (Vt). • A p-depletion layer have more holes than p-substrate since its electrons have been pushed into the inversion layer. • Does not conduct when Vgs<Vt (Cut-off).

18. Enhancement NMOS V

19. Enhancement NMOS - VI • When Vgs>Vt, the inversion layer (n channel) becomes thicker. • The horizontal electrical field due to Vds moves electrons from the source to the drain through the channel. • If Vds=0, the channel is formed but not conduct.

20. Case when Vds=0

21. Linear Region

22. Linear Region - II • When Vgs>Vt and Vgd>Vt, the inversion layer increases in thickness and conduction increases. • The reason is that there are non-zero inversion layer at both source and drain (our previous analysis works for both Vgs and Vgd).This is called linear region. • Vgd>Vt means that Vgd=Vgs-Vds>=Vt, i.e., Vds<=Vgs-Vt • Vds>0 • Ids depends on Vg, Vgs, Vds and Vt.

23. Saturation Region

24. Saturation Region - II • When Vgs>Vt and Vgd<Vt, we have non-zero inversion layer at source but zero inversion layer at drain. • Inversion layer is said to be pinched off. This is called the saturation region. • Vgd<Vt means that Vgs-Vds<Vt, i.e., Vds>Vgs-Vt. • Electrons leaves the channel and moves to drain terminal through depletion region.

25. Summary • Three regions of conduction • Cut-off: 0<Vgs<Vt • Linear: 0<Vds<Vgs-Vt • Saturation: 0<Vgs-Vt<Vds • Vt depends on gate and insulator materials, thickness of insulators and so forth – process dependant factors, and Vsb and temperature – operational factors.

26. PMOS

27. PMOS - II • Dual of NMOS • Three regions of conduction • Cut-off: 0>Vgs>Vt • Linear: 0>Vds>Vgs-Vt • Saturation: 0>Vgs-Vt>Vds • Current computation is the same as NMOS except that the polarities of all voltages and currents are reversed. • Mobility in PMOS is usually half of the mobility in NMOS due to process technology.

28. I-V characteristics (different Vt)

29. I-V Characteristics II

30. Wire

31. Modern Interconnect

32. Modern Interconnect - II

33. Interconnect Delay Dominates 300 250 Interconnect delay 200 150 Delay (psec) 100 Transistor/Gate delay 50 0 0.25 0.8 0.5 0.35 0.25 0.18 0.15 Technology generation (m) Source: Gordon Moore, Chairman Emeritus, Intel Corp.

34. Capacitor • A capacitor is a device that can store an electric charge by applying a voltage • The capacitance is measured by the ratio of the charge stored to the applied voltage • Capacitance is measured in Farads

35. 3D Parasitic Capacitance • Given a set of conductors, compute the capacitance between all pairs of conductors. 1V + - - + + + - C=Q/V - + - - -

36. Simplified Model • Area capacitance (Parallel plate): area overlap between adjacent layers/substrate • Fringing/coupling capacitance: • between side-walls on the same layer • between side-wall and adjacent layers/substrate m3 m2 m2 m2 m1

37. The Parallel Plate Model (Area Capacitance) Capacitance is proportional to the overlap between the conductors and inversely proportional to their separation

38. Wire Capacitance • More difficult due to multiple layers, different dielectric =8.0 m3 multiple dielectric =4.0 m2 m2 m2 =3.9 =4.1 m1

39. Simple Estimation Methods • C = Ca*(overlap area) +Cc*(length of parallel run) +Cf*(perimeter) • Coefficients Ca, Cc and Cf are given by the fab • Cadence Dracula • Fast but inaccurate

40. Accurate Methods In Industry • Finite difference/finite element method • Most accurate, slowest • Raphael • Boundary element method • FastCap, Hicap

41. Wire Resistance • Basic formula R=(/h)(l/w) •  : resistivity • h: thickness, fixed for a given technology and layer number • l: conductor length • w: conductor width l h w

42. Analysis of Simple RC Circuit i(t) R v(t) vT(t) C ± state variable Input waveform

43. v0u(t) v0 v0(1-e-t/RC)u(t) Analysis of Simple RC Circuit Step-input response: match initial state: output response for step-input:

44. 0.69RC • v(t) = v0(1 - e-t/RC) -- waveform under step input v0u(t) • v(t)=0.5v0  t = 0.69RC • i.e., delay = 0.69RC (50% delay) v(t)=0.1v0 t = 0.1RC v(t)=0.9v0 t = 2.3RC • i.e., rise time = 2.2RC (if defined as time from 10% to 90% of Vdd) • Elmore Delay TD = 0.69 RC

45. Elmore Delay • 50%-50% point delay • Delay=0.69RC Delay

46. Delay

47. Elmore Delay - III What is the delay of a wire?

48. Elmore Delay – IV Assume: Wire modeled by N equal-length segments For large values of N: Precisely, should be 0.69RC/2

49. Elmore Delay - V n2 n1 n1 n2 C/2 C/2 R R=unit wire resistance*length C=unit wire capacitance*length

50. RC Tree Delay 4 4 2 2 7 2 7 24+4*2=32 3.5 1 2 1 3.5 Unit wire cap=1, unit wire res=1 2*(1+3.5+3.5+2+2)=24 24+7*3.5=48.5 Precisely, 0.69*48.5 RC Tree Delay=max{32,48.5}=48.5