1 / 28

Analisis Rangkaian Digital

Analisis Rangkaian Digital. Sistem Komputer Universitas Narotama. Topik 5 – Desain Rangkaian Kombinasional. Task: Given a description of problem (logical statement), find the corresponding digital circuits that produce the output (answer) given a set of inputs (condition). Contoh-2:

mliss
Download Presentation

Analisis Rangkaian Digital

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. AnalisisRangkaianDigital SistemKomputer UniversitasNarotama

  2. Topik 5 – Desain Rangkaian Kombinasional • Task: Given a description of problem (logical statement), find the corresponding digital circuits that produce the output (answer) given a set of inputs (condition). • Contoh-2: • Parking lot controller • Elevator controller • Prime number indicator • Adder, subtractor, …

  3. Brute-force approach Row N3 N2 N1 N0 F 0 0 0 0 0 0 1 0 0 0 1 1 2 0 0 1 0 1 3 0 0 1 1 1 4 0 1 0 0 0 5 0 1 0 1 1 6 0 1 1 0 0 7 0 1 1 1 1 8 1 0 0 0 0 9 1 0 0 1 0 10 1 0 1 0 0 11 0 0 1 1 1 12 1 1 0 0 0 13 1 1 0 1 1 14 1 1 1 0 0 15 1 1 1 1 0 • Design: given a description or truth table, find the corresponding Boolean expression and digital circuit. • Brute-force design methodology: • Truth table  canonical sum •  SoP or sum of minterms •  AND-OR / NAND-NAND • Example: prime number detector F = SN3N2N1N0(1,2,3,5,7,11,13)

  4. Minterm list -> canonical sum

  5. Algebraic simplification • Recall (T8) X · Y + X · Y’ = X • Simplify equation to reduce number of gates & gate inputs

  6. Resulting circuit

  7. Combinational circuit design/minimization • Objective: • Minimizing # logic gates • Minimizing # inputs to the logic gates • Note different logic gates may have different # transistors • General idea: simplify the Boolean expression using the theorems, especially (T10, T10’, T13, T13’) • Karnaugh-map (K-map) • Graphical representation of the truth table • Offers visualization of (T10, T10’) • Works for functions with less than 6 variables • Real world: use programs to minimize logic circuits • E.g., VHDL, Verilog, ABEL, …

  8. Karnaugh-map usage • Plot 1s corresponding to minterms of function. • Circle largest possible rectangular sets of 1s. • # of 1s in set must be power of 2 • OK to cross edges • Read off product terms, one per circled set. • Variable is 1  include variable • Variable is 0  include complement of variable • Variable is both 0 and 1  variable not included • Circled sets and corresponding product terms are called `prime implicants’ • Minimum number of gates and gate inputs

  9. 3 variable example: F = S(1,2,5,7) • Rules of thumb: • Group (prime implicant) as large (many 1s) as possible • As few groups as possible • Overlaps are OK

  10. 4 variable K-map example Note how it maps to the rows of the truth table

  11. Prime-number detector revisited

  12. Compare with the previous circuit • When we solved algebraically, we missed one simplification- the circuit below has three less gate inputs.

  13. Design example: alarm controller • Problem statement: • The ALARM output is 1 if PANIC is 1, or if ENABLE is 1 and the house is not secure. • The house is secure if WINDOW, DOOR, GARAGE are all 1 • This can be put in logic expressions as follows: ALARM = PANIC + ENABLE · SECURE’ SECURE = WINDOW · DOOR · GARAGE ALARM = PANIC + ENABLE · (WINDOW · DOOR · GARAGE)’ Multiply out and use (T13), we get the SoP form ALARM = PANIC + ENABLE · WINDOW’ + ENABLE · DOOR’+ ENABLE · GARAGE’

  14. K-map with don’t-cares • In some cases, the output of a combinational circuit doesn’t matter for certain input combinations. • Such combinations are called don’t-cares and the output is represented in the truth table and K-maps as `d’. • When using K-maps to minimize such functions: • Allow d’s to be included when grouping sets of 1’s to make the sets as large as possible. • Do not circle any set that only contains d’s.

  15. N3 N3’· N0 N3 N2 N2 · N0 00 01 11 10 N1 N0 12 8 0 4 00 01 11 10 d 13 5 9 1 d 1 1 N0 15 7 11 3 1 1 d d N1 14 2 10 6 1 d d N2’· N1 N2 Example with don’t-cares • Prime number detection for BCD numbers (takes value between 0-9) – minterms 10-15 are treated as don’t-cares: F(N3,N2,N1,N0) = SN3,N2,N1,N0 (1,2,3,5,7) + d(10,11,12,13,14,15) From K-map: Prime Implicants: N3’· N0 N2’· N1 N2 · N0 Distinguished 1-cells: Cell 1 covered by N3’· N0 Cell 2 covered by N2’· N1 Here not all prime implicants are essential prime implicants that must be included minimum SOP expression: F = N3’ · N0 + N2’ · N1

  16. W W WX WX 00 01 11 10 00 01 11 10 YZ YZ 12 28 8 24 0 16 20 4 00 01 11 10 00 01 11 10 29 13 5 21 25 9 1 17 Z Z 31 15 23 7 11 27 19 3 Y Y 30 14 18 2 26 10 22 6 V = 0 V = 1 X X 5-variable K-maps • The K-map for a 5-variable logic function is organized as two 4-variable K-maps: • Can be visualised as being one 4-variable map on top of another 4-variable map

  17. W W WX WX 00 01 11 10 00 01 11 10 YZ YZ 28 12 24 8 0 16 20 4 00 01 11 10 00 01 11 10 29 13 21 5 25 9 17 1 Z Z 31 15 7 23 11 27 19 3 Y Y 14 30 18 2 26 10 22 6 V = 0 V = 1 X X 5-variable K-map example • F(V,W,X,Y,Z) = SV,W,X,Y,Z(4,5,6,7,9,11,13,15,25,27,29,31) 1 1 1 1 1 1 1 1 1 1 1 1

  18. W W WX WX 00 01 11 10 00 01 11 10 YZ YZ 12 28 8 24 0 16 4 20 1 00 01 11 10 00 01 11 10 1 1 1 13 29 5 21 1 9 25 1 1 17 Z Z 1 31 15 23 7 1 1 1 1 27 11 19 3 Y Y 30 14 1 18 2 10 26 6 22 V = 0 V = 1 X X W · Z V’ · W’· X 5-variable K-map example – cont. Minimum SOP: F = V’ · W’· X + W · Z

  19. K-map product-of-sum minimization • Using K-map, find a minimal PoS expression for F(X,Y,Z) = PX,Y,Z (0,3,4,7) Truth Table X XY Row X Y Z F 0 0 0 0 0 1 0 0 1 1 2 0 1 0 1 3 0 1 1 0 4 1 0 0 0 5 1 0 1 1 6 1 1 0 1 7 1 1 1 0 00 01 11 10 Z 6 0 2 4 0 0 0 1 3 5 7 1 0 0 Z Y

  20. (Y + Z) X XY 00 01 11 10 Z 6 0 2 4 0 1 0 0 3 5 7 1 0 0 Z Y (Y’ + Z’) K-map PoS minimization – cont. Truth Table Row X Y Z F 0 0 0 0 0 1 0 0 1 1 2 0 1 0 1 3 0 1 1 0 4 1 0 0 0 5 1 0 1 1 6 1 1 0 1 7 1 1 1 0 Minimum PoS:F = (Y + Z) · (Y’ + Z’)

  21. W WX 00 01 11 10 YZ 12 8 0 4 0 0 00 01 11 10 13 5 9 1 0 0 Z 15 7 11 3 0 0 Y 14 2 10 6 0 0 X K-map PoS minimization – another example • Using K-map, find a minimal POS expression for • F(W,X,Y,Z) = PW,X,Y,Z (1,3,8,10,12,13,14,15)

  22. W WX 00 01 11 10 YZ (W’ + Z) 12 8 0 4 0 0 00 01 11 10 13 5 9 1 0 0 (W + X + Z’) Z 15 7 11 3 0 0 Y 14 2 10 6 0 0 (W’ + X’) X K-map PoS minimization – another example Minimum POS: F = (W + X + Z’) · (W’ + Z) · (W’ + X’)

  23. Timing Diagram propagation delay 1 X 0 X X’ 1  0 1 X’ 0 Transient output Steady-state output Time Combinational Circuit: Transient vs. Steady-state Output • Transient output: the temporary output due to the gate propagation delay(s) • Gate propagation delay: the time it takes to pull up (or down) the output signals due to the change at the input – depends on the transistor level implementation.

  24. Static-0 Hazard Static-1 Hazard 1 1 1 1 1 0 0 0 0 0 Dynamic Hazard Example Hazards in combinational circuits • Output glitch: a momentary (transient) fluctuation in output signal due to changes in input signal. • Static hazards: • Static-0 hazard: The output should be 0 but goes momentary to 1 as a result of an input change – possible in AND-OR circuits • Static-1 hazard: The output should be 1 but goes momentary to 0 as a result of an input change – possible in OR-AND circuits • Dynamic hazards:The output changes more than once as a result of a single input change (impossible in 2-level circuits).

  25. 1 X X · Z’ Z’ Z 0 ® 1 1 ® 0 X 1 Z XY F 0 Time 00 01 11 10 Z 1 ® 0 D 6 0 2 4 1 0 1 Z’ 0 1 Y Y · Z 3 5 7 1 Z 1 Y·Z 0 1 1 Y D X·Z’ 0 0 X · Z’ 1 1 Steady-state output D 1 1 F Y · Z Example: static-1 hazard • A static-1 hazard exists in the following AND-OR circuit when X=1, Y=1 and Z changes from 1 to 0 (assume all gates have propagation delay D) Extra propagation delay between Z and Z’ Circuit Timing Diagram 1 ® 0 ® 1 K-map

  26. X X·Y 00 01 11 10 Z 6 0 2 4 X 0 1 X · Z’ Z’ 3 5 7 1 Z Z X · Y F Y X·Z’ Y Y · Z 1 1 1 Y·Z 1 X·Y Eliminate static-1 hazard using K-map • Static-1 hazards are found using k-maps by finding adjacent 1 cells that are covered by different product terms. • To eliminate static-1 hazards, additional product terms (prime implicants) are needed to cover such cells thus covering the transition of the variable causing the hazard. • For the previous example the static-1 hazard is eliminated by including the additional product term X · Y New F = X · Z’ + Y · Z + X · Y

  27. Eliminate static-0 hazard using K-map • A static-0 hazard occurs in OR-AND circuits when an input variable and its complement are connected to two different OR gates. • The procedure to find and eliminate static-0 hazards using K-maps is done in a dual way to finding static-1 hazards. • Static-0 hazards are found using k-maps by finding adjacent 0 cells that are covered by different sum terms. • To eliminate static-0 hazards, additional sum terms (prime implicates) are needed to cover such cells thus covering the transition of the variable causing the hazard.

  28. Homework #2 • Turn in: (show your steps) • 4.13 (f), 4.14 (f) • 4.19 (e), 4.20 (e), 4.21 (e) • 4.22 (d) • 4.45 • 4.47 (refer to 4.46 for hints) • 4.55 (a) (b) (c) • 4.65 • 4.72 (f), 4.73 (f) • Self exercise: (you do not need to turn in these, but think about them!!) • 4.48, 4.50, 4.52, 4.68, 4.71, 4.84, 4.85

More Related