Environment for Model-Integrated Adaptive Computing ATR Application Scenario

1. Model-Integrated Environment for Adaptive ComputingJason ScottTed BaptyInstitute for Software Integrated SystemsVanderbilt University

2. Environment for Model-Integrated Adaptive ComputingATR Application Scenario Free-Flight Target Acq. Civilian/Friendly Target Target Re-Acq. Target ID,Mid Range Tracking Target Acq./ Lock-on Locked-On Long Range Tracking Short Range Track Target Obstruction: Target Loss Target Re-Acq. AimPoint Selection Time/ MFLOPS Latency Many Small Targets Few Large Targets Throughput Moderate Power High Power Very Low Power

3. DARPA ACS ProgramMICOM/Vanderbilt Cooperation ATR Domain Info Algorithms Testing Techniques Data Sets Hardware MICOM Vanderbilt Modeling Technology System Integration Tech Reconfiguration Tech Software Tools

4. Sequence of Filters MICOM ATR Algorithms FFT Chip on Custom Board Sensor FFT IFFT X  Gate Comp X + X.5 X Conv. (Var Size) X2 + Software on Parallel Processor Future:Fixed FPGA Design Conv. (Var Size) X2

5. Observations • ATR Application Requires… • Adaptable Power Consumption • Minimize Hardware Envelope • Varying Performance Goals per Mode • Latency/Throughput/Accuracy • Reconfigurable Approach • Re-Allocate Hardware Matching Demand • Minimize Hardware Redundancy • Maximize Component Utilization • Allow Selective Usage for Power Mgt.

6. FPGA FPGA as PostProc FPGA as PostProc FPGA as PostProc FPGA as PostProc FPGA as PostProc FPGA as PostProc FPGA as PostProc Architecture Variations Higher Accuracy Arithmetic Needed ASIC Shared I/FFT & Conv ASIC Shared I/FFT & Conv ASIC FFT/IFFT ASIC FFT/IFFT DSP DSP Larger Convolutions Smaller Convolutions FPGA as I/O FPGA as Control FPGA as I/O FPGA as Control FPGA as XBAR RISC RISC FPGA as I/O FPGA as Accelerator and I/O Filter Memory Many Targets Fewer Targets Filter Memory DSP DSP DSP • Characteristics: • High Throughput • Longer Latency Permitted • Very Adaptable/Moderate Power • Characteristics: • Highest Power • Fixed Function • Minimum Latency/Highest Performance Smaller Latency Target Loc Target Location Target Loc VLIW DSP VLIW DSP Filter Many Targets DSP DSP DSP High Latency Variable Conv. Low Throughput Variable Conv Size Variable # Targets FPGA as I/O FPGA as XBar FPGA as I/O FPGA as I/O FPGA Dpath/Ctrl FPGA as XBAR RISC RISC ASIC Filter Memory Low-Mid Latency FPGA as Accelerator and I/O High Throughput Target Loc Filter Memory DSP Low-Power Shutdown Characteristics: Lowest Power, Flexible/Max Latency/Lowest Perf • Characteristics: • High Throughput/Latency/Adaptable/Moderate Power

7. Implementation Strategies • Common/Uniform Execution Environment • HW/SW Run-Time Environment • Abstraction of Architectural Details • High-Level/Domain-Specific Modeling • System Synthesis From Models • Constraint Networks For Design-Space Search Min • Goals: • Maximize use of Libraries • Maximize Flexibility of Implementation • Support Technology Migration

8. Environment for Model-Integrated Adaptive ComputingProject Goal MODELS Mission Models MODEL BUILDER TOOLS MODEL ANALYSIS TOOLS MODEL-INTEGRATED DEVELOPMENT ENVIRONMENT ATR Arcitecture Models Hardware Resource Models GENERATORS SW GEN. HW GEN. RUNTIME ENVIRONMENT ATR

9. Modeling Concepts

10. Modeling ParadigmStructural/Algorithmic Description Compound Compound Primitive Template Software Hardware Compound Primitive

11. Modeling ParadigmStructural Algorithm Description Long Range Track Algorithm Alternatives Spatial Domain Spectral Domain Sensor Sensor Preprocess Filter Preprocess 2D FFT Image DB XCorr Img Spec DB Mult Error Comp Error Comp Guidance Loss of Track Guidance Loss of Track

12. Software on 1 DSP Software on N DSPs X P0 P1 Pn P0 P1 Pn Modeling ParadigmStructural Algorithm Description (2) 2D-FFT Implementation Alternatives Attributes Performance(Accuracy, Speed, Power) Resources (Power/Size/User Defined) Hardware on FPGA

13. Modeling ParadigmResource Models Networks Processors FPGAs Core Ports Core Ports

14. Modeling Paradigm Behavioral Description: Hierarchical State Machine Transition Rules Mode A Mode B Transition Rules Transition Rules Transition Rules Mode C Attributes Algorithms Performance Specs Constraints (Power/Size/User Defined)

15. Execution Environment

16. Common Execution Semantics Asynchronous Communication Buffer Worker function Comm Comm Software Hardware SW Process HW Process Stream Stream FIFO FIFO Queue in kernel Hardware FIFO

17. Resource Model + Communication Interfaces C40 DSP XC4010 FPGA HOST PC ASIC IFC P1 STREAMS IFC - BIDIR BIDIR IFC P1 P2 P2 P3 Multiple Data Streams IN IFC OUT IFC OUT IFC IN IFC P1 STREAMS IFC OUT IN IFC P1 P2 DATA I/O P2 STREAMS IFC IN OUT IFC P3 C40 DSP XC6200 FPGA

18. Reconfiguration Manager Reconfig. Manager State Tables Schedules/Maps FPGA Configs Run-Time Reconfiguration Support Environmental Stimulus Library Schedule & Comm Mapping FPGA Config RAM Memory Manager Scheduler Comm Hardware Device Drivers Kernel Virtual Hardware Kernel Software Hardware

19. System Synthesis

20. Evaluate Algorithm Alternatives Evaluate Algorithm Alternatives Evaluate Algorithm Alternatives Evaluate Implementation Alternatives Evaluate Implementation Alternatives Evaluate Implementation Alternatives Performance Estimation Performance Estimation Performance Estimation Synthesis Synthesis Synthesis System SynthesisTop-Down System Construction Increasing Resolution Evaluate State Behavior Synthesize System Mgr State Tables Synthesize Hardware (VHDL) Synthesize Interfaces Synthesize Software(Dflow)

21. Behavior/Requirements Algorithm Dataflow Design Alternatives HW/SW Implementations Implementation Constraints Design Flow / Tool Interaction Models Configuration Evaluation Process MIC Editor Best Solutions Missile Designer Algorithm Designer Hardware Engineer Software Engineer Runtime System Generator FPGA Implementation SW/HW Assign Behavorial States Synth/Elab. SW Libs HW Libs (VHDL) Log. Sim Place/Route Schedule/Comm Generator Reconfig Mgr Synthesis Time Sim Bitfile Gen Runtime System

22. Reference Platforms

23. C40 (DSP) C40 (DSP) C40 (DSP) C40 (DSP) C62/67 (DSP) C62/67 (DSP) Altera FPGA Altera FPGA Reference Platform IConfigurable Topology PCI Bus A/D Conv Xilinx 4010 FPGA A/D Conv Xilinx 4010 FPGA A/D Converter from NASA Project Dynamically Reconfigurable FPGA Board Xilinx 4013 FPGA Xilinx 6264 FPGA Configuration Manager Intel Pentium

24. Reference Platform IITopology + Reconfig. Computation Parallel DSP’s FPGAs (Processing) ATR Data In Control Signals Out Data Storage High Speed Data I/O Memory FPGAs (Xilinx/Altera) TI 320C4x/6x Xilinx 6200 FPGA’s Xilinx 6200 FPGA Intel Pentium Conventional Processors Reconfigurable Data Paths Reconfigurable Computing Elements PCI Bus Configuration Manager Intel Pentium

25. Reference Platform IIIFull-Scale Adaptive Computing Parallel DSP’s FPGAs (Processing) ATR Data In Control Signals Out Data Storage High-Speed Coprocessors High Speed Data I/O Memory ASIC Engines (Plessey/TRW) TMS320C40 TMS320C62/67 FPGAs (Xilinx/Altera) Xilinx 62xx FPGA’s Xilinx 62xx FPGA Intel Pentium Conventional Processors Reconfigurable Data Paths Reconfigurable Computing Elements Configuration Manager Intel Pentium

26. Research Issues • Reconfiguration • Synchronization: Maintaining Consistency • Data Flow/Algorithm: Correct Outputs • Real-Time: Maintaining Deadlines • Synthesis & Optimization of Solutions • Minimizing Search Space • Maximizing Performance Metrics • Definition of Modeling Paradigm • Natural to Users • Powerful Enough to Express Requirements