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CMOS Analog Addition/Subtraction

CSE598A/EE597G Spring 2006. CMOS Analog Addition/Subtraction. Jaehyun Lim, Kyusun Choi Department of Computer Science and Engineering The Pennsylvania State University. Addition. Why adder? Neural network Continuous time signal processing application Low power / small size.

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CMOS Analog Addition/Subtraction

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  1. CSE598A/EE597G Spring 2006 CMOS Analog Addition/Subtraction Jaehyun Lim, Kyusun Choi Department of Computer Science and Engineering The Pennsylvania State University

  2. Addition • Why adder? • Neural network • Continuous time signal processing application • Low power / small size

  3. Addition / Subtraction Using Op-Amp R2 Rf V2 R1 V1 = -Rf ( V1/R1 + V2/R2) R1 R2 V2 R1 = R2/R1 ( V1 - V2 ) V1 R2

  4. Addition / Subtraction Using Op-Amp R1 R2 V1 R3 V2 R1 V3 = R2/R1 ( V3 – V1 ) + R2/R3 ( V4 – V2 ) R3 V4 R2

  5. Other OP-Amp Applications • differentiator / integrator • active filters • I / V converter • positive / negative voltage reference • voltage supply • wave form generator • oscillator • and more…and more…and more…

  6. V2/2 + VS V1/2 + VS -V2/2 + VS -V1/2 + VS Vx Vy Addition • Design #1

  7. Addition • Design #1  : turn on Two conditions : saturation

  8. Addition • Design #2

  9. Addition • Design #2 

  10. Addition • Design #3 (Similar to Design #1)

  11. Subtraction • Design #1 (from adder Design #2)

  12. Subtraction • Design #1 

  13. Reference [1] M. Al-Nsour, et al., “Analog Computational Circuits for Neural Network Implementation,” Proceedings of ICECS '99. The 6th IEEE International Conference on Volume 1,  5-8 Sept. 1999 pp. 299 - 302 vol.1 [2] S. W. Tsay and R. W. Newcomb, “A Neural-Type Pool Arithmetic Unit,” Circuits and Systems, 1991., IEEE International Sympoisum on 11-14 June 1991 pp. 2518 - 2521 vol.5 [3] A. Diaz-Sanchez, et al., “A Compact High Frequency VLSI Differential Analog Adder,” Circuits and Systems, 1996., IEEE 39th Midwest symposium on Volume 1,  18-21 Aug. 1996 pp. 21 - 24 vol.1 [4] H. Chaoui, “CMOS Analogue Adder,” Electronics Letters Volume 31,  Issue 3,  2 Feb. 1995 pp. 180 – 181 [5] C. Chang, et al., “Low-Voltage Analog Tripler Circuit,” Journal of Analog Integrated Circuits and Signal Processing, vol. 26, pp. 125-128, Feb. 2001. [6] R. Fried and C. Enz, “A Family of Very Low-Power Analog Building Blocks Based on CMOS Translinear Loops,” Analog and Mixed IC Design, 1997. Proceedings., 1997 2nd IEEE-CAS Region 8 Workshop on 12-13 Sept. 1997 pp. 73 – 78 [7] “An Applications Guide for Op Amps,” National Semiconductor Application Note 20, Feb. 1969 [8] G. Clayton and Steve Winder, “Operational Amplifiers,” Newnes, 2003

  14. Simulation R1 R2 V1 R3 V2 R1 V3 = R2/R1 ( V3 – V1 ) + R2/R3 ( V4 – V2 ) R3 V4 2-stage diff amp R1=R2=R3=100 KΩ Addition: V1=V2=0 V Subtraction: V4=V2=0 V R2

  15. Simulation (1.50460 V) (2.25000 V)

  16. Simulation (1.00000 V) (0.50000 V) (0.00000 V)

  17. Simulation

  18. Simulation M1~M4: 1.98µ/0.48µ M5, M6: 26.64µ/0.48u

  19. Simulation -0.16 V 0.00 V 0.16 V

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