Overview

1. Overview • Why VLSI? • Moore’s Law. • The VLSI design process. These lecture notes include my annotations, changes and additions. These annotations, changes, and additions marked in red are not in any way endorsed or approved by the author or publisher of the text, Modern VLSI Design/System-on-Chip Design. A. Yavuz Oruc, University of Maryland, College Park, MD 20742

2. Why VLSI? • Integration improves the design and fabrication: • lower parasitics (capacitive charging, resistive dissipation) = higher speed; • lower power (smaller devices+ less heat dissipation at the interface); • physically smaller. • Integration reduces manufacturing cost-(almost) no manual assembly. • Integration also increases system reliability by reducing component interface and interconnections

3. VLSI and you • Microprocessors: • personal computers; • microcontrollers. • Hand-held devices-wireless phones, pdas,video cameras,etc… • DRAM/SRAM Memory chips • Special-purpose processors.

4. Moore’s Law • Gordon Moore: co-founder of Intel • Predicted that number of transistors per chip would grow exponentially (double every 18 months). • Exponential improvement in technology is a natural trend: steam engines, dynamos, automobiles.

5. Moore’s Law(Cont’d) • Q(n) = 2  Q(n-1.5) => • Q(n) = 2k Q(n-1.5k), • Q(0) = Q0 (some initial value at some initial date) => k= n/1.5 and • Q(n) = Q0  2n/1.5 = Q0  2n/1.5 • = Q0  (1.333)n • If we replace 1.5 by 1 we get a much steeper rise (2n). (Count doubles every year…)

6. Moore’s Law(Cont’d)

7. Moore’s Law(Cont’d) ftp://download.intel.com/museum/Moores_Law/Printed_Materials/Moores_Law_Backgrounder.pdf For a more complete list of intel processors and their features, seehttp://en.wikipedia.org/wiki/List_of_Intel_microprocessors

8. Moore’s Law(Cont’d)

9. Moore’s Law plot Log # transistors This is a log plot--- Taking the log of the formula for Q(n) gives a linear relation between the years and log of number of transistors: Log Q(n) = Log Q0 + n Log 1.333 (See slide 5)

10. The cost of fabrication • Current cost: $2-3 billion. • Typical fab line occupies about 1 city block, employs a few hundred people. • Most profitable period is first 18 months-2 years.

11. Cost factors in ICs • For large-volume ICs: • packaging is largest cost; • testing is second-largest cost. • For low-volume ICs, design costs may swamp all manufacturing costs.

12. The VLSI design process • May be part of larger product design. • Major levels of abstraction: • specification; (describe functionality) • architecture; (describe functionality with building blocks) • logic design; (convert architecture to logic circuits) • circuit design; (convert logic logic circuits to transistor circuits) • layout. (lay out the transistor circuits in VLSI)

13. Challenges in VLSI design • Multiple levels of abstraction: transistors to CPUs. • Multiple and conflicting constraints: low cost and high performance are often at odds. • Short design time: Late products are often irrelevant.

14. Dealing with complexity • Divide-and-conquer: limit the number of components you deal with at any one time. • Group several components into larger components: • transistors form gates; • gates form functional units; • functional units form processing elements; • etc.

15. Hierarchical name • Interior view of a component: • components and wires that make it up. • Exterior view of a component = type: • body; • pins. cout Full adder sum a b cin

16. Add2.a Add1.a Instantiating component types • Each instance has its own name: • add1 (type full adder) • add2 (type full adder). • Each instance is a separate copy of the type: cout Add2(Full adder) Add1(Full adder) sum sum a a b b cin cin

17. A hierarchical logic design Incomplete--- not enough labels to specify the netlist and component list on the next slide (Component terminal counts do not appear to match either!) box1 box2 x z

18. Net list: (list of terminals in a net) net1: top.in1 in1.in net2: i1.out xxx.B topin1: top.n1 xxx.xin1 topin2: top.n2 xxx.xin2 botin1: top.n3 xxx.xin3 net3: xxx.out i2.in outnet: i2.out top.out Component list (nets connected to each pin of a component): top: in1=net1 n1=topin1 n2=topin2 n3=topin3 out=outnet i1: in=net1 out=net2 xxx: xin1=topin1 xin2=topin2 xin3=botin1 B=net2 out=net3 i2: in=net3 out=outnet Net lists and component lists

19. A hierarchical logic design p i1 i1 o1 o1 s i1 A B C o1 N i1 o1 i2 o2 t i2 o2 top q r Inserted & modified the labels

20. Two-level net list: Level-1has 2 components, top and C, which appear on 6 nets: net11: top.p net12: top.q net13: top.r net14: top.s, C.i1 net15: top.t C.i2 net16: C.o1 Level-2 has 3 components: A, N and B, which appear on 7 nets net21: top.p, A.i1 net22: top.q, A.o2 net23: top.r, B.i2 net24: top.s, B.o1 net25: top.t, B.o2 net26: A.o1, N.i1 net27: B.i1, N.o1 Two-level component list Level-1 has 2 components, top and C and they are on the following nets: top = net11, net12, net13,net14,net15 C= net15, net16 Level-2 has 3 components, A, N, and B, and they are on the following nets A = net21, net22 B = net23, net24, net25 N = net26, net27 Net lists and component lists

21. Component hierarchy top i1 xxx i2

22. Hierarchical names • Typical hierarchical name: • top/i1.foo component pin

23. Layout and its abstractions • Layout for dynamic latch: (Top view)

24. Stick diagram

25. Transistor schematic

26. Mixed schematic inverter

27. Levels of abstraction • Specification: function, cost, etc. • Architecture: large blocks. • Logic: gates + registers. • Circuits: transistor sizes for speed, power. • Layout: determines parasitics.

28. Circuit abstraction • Continuous voltages and time:

29. Digital abstraction • Discrete levels, discrete time: Least significant bit 1 + 1 = 2

30. Register-transfer abstraction • Abstract components, abstract data types: 0010 + 0001 + 0111 0100

31. Top-down v.s. bottom-up design • Top-down design adds functional detail. • Create lower levels of abstraction from upper levels. • Bottom-up design creates abstractions from low-level behavior. • Good design needs both top-down and bottom-up efforts.

32. English Throughput, design time Executable program Function units, clock cycles function Sequential machines cost Literals, logic depth Logic gates Nanoseconds power transistors microns rectangles Design abstractions specification behavior register- transfer logic circuit layout

33. Design validation • Must check at every step that errors haven’t been introduced-the longer an error remains, the more expensive it becomes to remove it. • Forward checking: compare results of less- and more-abstract stages. • Back annotation: copy performance numbers to earlier stages.

34. Manufacturing test • Not the same as design validation: just because the design is right doesn’t mean that every chip coming off the line will be right. • Must quickly check whether manufacturing defects destroy function of chip. • Must also speed-grade.

35. Problem 1.1. At the Intel site, http://www.intel.com/pressroom/kits/quickrefyr.htm, the clock speeds of intel family of microprocessors from 1971 to 2004 are listed. Use this list to fit the clock speeds of Intel microprocessors that were manufactured between 1971 and 2004 by a power function, i.e., determine the base b in f0bn, where f0 is the clock speed in MHz in 1971 and n denotes a year between 1971 and 2004. if more than one processor is listed within a given month, use the clock speed of the fastest processor. Plot the actual clock speeds v.s. the power function you have derived. Problem 1.2. Give the net and component lists for the following circuit by clearly marking each of the nets and components. Vd input-1 A input-2 output B C Vs Vs Homework Set-1(Due: September 19) D