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Operating Systems

Operating Systems. Certificate Program in Software Development CSE-TC and CSIM, AIT September -- November, 2003. Objectives describe some of the memory management schemes used by an OS so that several processes can be in memory (RAM) at once. 8. Memory Management (Ch. 8, S&G).

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Operating Systems

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  1. Operating Systems Certificate Program in Software DevelopmentCSE-TC and CSIM, AITSeptember -- November, 2003 • Objectives • describe some of the memory management schemes used by an OS so that several processes can be in memory (RAM) at once 8. Memory Management(Ch. 8, S&G) ch 9 in the 6th ed.

  2. Contents 1. Background 2. Logical vs. Physical Address Spaces 3. Swapping 4. Partition Allocation 5. Paging 6. Segmentation

  3. 1. Background Fig. 8.1, p.241;VUW CS 305 compile tme load time execution Source Object LoadModule ExecutableImage Compiler Linker Loader DynamicLibraries ObjectLibraries SystemLibraries

  4. 1.1. Address Binding • compile time • the compiler knows where a process will reside in memory so generates absolute code (code that starts at a fixed address) • load time • the compiler does not know where a process will reside so generates relocatable code (its starting address is determined at load time) continued

  5. execution time • the process can move during its execution, so its starting address is determined at run time

  6. 1.2. Dynamic Loading • A routine (function, procedure, library, etc.) is not loaded until is is called by another program • the routine must be stored as relocatable code • Unused routines are never loaded • saves space

  7. 1.3. Dynamic Linking • Often used for system libraries • e.g. Dynamically Linked Libraries (DLLs) • The first call to a DLL from a program causes the linking in and loading of the libraries • i.e. linking/loading is determined at run time continued

  8. Allows libraries to be changed/moved since linking/loading information is not fixed (as much) in the calling program.

  9. 1.4. Overlays • Keep in memory only those pieces of code that are needed at any given time • saves space • Example: a two-pass assembler • Pass 1 70KPass 2 80KSymbol table 20KCommon routines 30K continued

  10. Loading everything requires 200K • Use two overlays: • A: symbol table, common routines, pass 1 • requires 120K • B: symbol table, common routines, pass 2 • requires 130K

  11. 3. Logical vs. Physical Address Space • The user sees a logical view of the memory used by their code • in one piece, unmoving • sometimes called a virtual address space • This is mapped to the physical address space • code may be located in parts/partition • some parts may be in RAM, others in backing store continued

  12. The mapping from logical to physical is done by the Memory Management Unit (MMU). • Hiding the mapping is one of the main aims of memory management schemes.

  13. Example: Dynamic Relocation Fig. 8.3, p.246 memory relocationregister 14000 logicaladdress physicaladdress CPU + 346 14346 MMU

  14. 3. Swapping • If there is not enough memory (RAM) for all the ready processes then some of them may be swapped out to backing store. • They will be swapped back in when the OS can find enough memory for them. continued

  15. Diagram Fig. 8.4, p.247 OS P1 swap out P2 swap in user space continued

  16. With compile time / load time address binding, the process must be swapped back to its old location • no such need for processes with execution time address binding • Must be careful not to swap out a process that is waiting for I/O.

  17. The Ready Queue • The ready queue consists of: • processes in memory that are ready to run • processes swapped out to backing store that are ready to run • they will need to be swapped back in if they are chosen by the CPU scheduler

  18. Swap Times • The speed of swapping affects the design of the CPU scheduler • the amount of execution time it gives to a process should be much greater than the swap time to bring it into memory

  19. Swap Time Example • Assume a transfer rate of 1MB/sec. • A transfer of 100K process will take: • 100/1000 = 100 ms • Total swap time: = transfer out + transfer in + (2 * latency) = 100 + 100 + (2 * 8) = 216 ms

  20. 4. Partition Allocation • Divide memory into a fixed no. of partitions, and allocate a process to each. • Partitions can be different fixed sizes. 16 16 32 64 128 continued

  21. Processes are allocated to the smallest available partition. • Internal fragmentation will occur:

  22. 4.1. Variable-size Partitions Fig. 8.7, p.252 0 OS Job Queue 400K process memory time P1 600K 10 P2 1000K 5 P3 300K 20 P4 700K 8 P5 500K 15 2160K user space 2560K

  23. Memory Allocation Fig. 8.8., p.253 0 0 OS OS 400K 400K P2ends P4allocated P1 P1 1000K 1000K P2 2000K 2000K P3 P3 2300K 2300K 2560K 2560K continued

  24. 0 0 OS OS 400K 400K P4allocated P1ends P5allocated P1 1000K 1000K P4 P4 1700K 1700K 2000K 2000K P3 P3 2300K 2300K 2560K 2560K continued

  25. 0 OS 400K P5allocated P5 externalfragmentation develops 900K 1000K P4 1700K 2000K P3 2300K 2560K

  26. 4.2. Dynamic Storage Allocation • Where should a process of size N be stored when there are a selection of partitions/holes to choose from? • First fit • allocate the first hole that is big enough • fastest choice to carry out continued

  27. Best fit • allocate the smallest hole that is big enough • leaves smallest leftover hole • Worst fit • allocate the largest hole • leaves largest leftover hole

  28. 4.3. Compaction Fig. 8.10, p.255 0 0 OS OS 400K 400K P5 P5 900K 900K 1000K P4 P4 1600K 1700K P3 2000K 1900K P3 2300K 2560K 2560K

  29. Different Strategies Fig. 8.11, p.256 0 0 OS OS 300K 300K P1 P1 500K 500K Version 1 600K P2 600K P2 P3 1000K 800K P3 P4 1200K 1200K 1500K P4 1900K 2100K 2100K original allocation moved 600K

  30. Or: 0 0 OS OS 300K 300K P1 P1 500K 500K Version 2 600K P2 600K P2 P4 1000K 1000K P3 1200K P3 1200K 1500K P4 1900K 2100K 2100K original allocation moved 400K

  31. Or: 0 0 OS OS 300K 300K P1 P1 500K 500K Version 3 600K P2 600K P2 1000K P3 1200K 1500K 1500K P4 P4 1900K 1900K P3 2100K 2100K original allocation moved 200K

  32. 5. Paging • Divide up the logical address space of a process into fixed size pages. • These pages are mapped to same size frames in physical memory • the frames may be located anywhere in memory

  33. 5.1. The Basic Method • Each logical address has two parts: < page number p, page offset d > • A page table contains the mapping from a page number to the base address of its corresponding frame. • Each process has its own page table • stored in its PCB

  34. p f d d Paging Hardware Fig. 8.12, p.258 physicaladdress logicaladdress physicalmemory CPU p f

  35. 5.2. Size of a Page • The size of a page is typically a power of 2: • 512 (29) -- 8192 (213) bytes • This makes it easy to split a machine address into page number and offset parts. continued

  36. For example, assume: • the address space is 2m bytes large • a page can be 2n bytes in size (n < m) • The logical address format becomes: page number n page offset d m-n n

  37. 5.3. Example p.258 • Address space is 32 bytes (25) • Page size: 4 bytes (22) • Therefore, there can be 8 pages (23) • Logical address format: page number n page offset d 3 2

  38. Fig. 8.14, p.260 physical memory 1620 a b c d24 e f g h28 04 i j k l8 m n o p12 0 a1 b2 c3 d4 e5 f6 g7 h8 i9 j10 k11 l12 m13 n14 o15 p logicalmemory 0 5 1 6 2 1 3 2 pagetable

  39. Using the Page Table • Logical Address Physical Address 0 (5*4) + 0 = 20 3 (5*4) + 3 = 23 5 (6*4) + 1 = 25 14 (2*4) + 2 = 10

  40. 5.4. Features of Paging • No external fragmentation • any free frame can be used by a process • Internal fragmentation can occur • small pages or large pages? • There is a clear separation between logical memory (the user’s view) and physical memory (the OS/hardware view).

  41. 5.5. Performance Issues • Every access must go through a page table • Small page table  registers • Large page table  table in memory • a memory access requires indexing into the page table and a memory access • Translation Look-aside Buffer (TLB) • sometimes called an “associative cache”

  42. f p d d 5.6. Paging with a TLB Fig. 8.16, p.264 logicaladdress physicaladdress physicalmemory CPU TLB hit p f TLB p f TLB miss

  43. Performance • Assume: • memory access takes 100 nsec • TLB access takes 20 nsec • A 80% hit rate: • effective access time is = (0.8 * 120) + (0.2 * 220) = 140 nsec • 40% slowdown in the memory access time TLB +page table +memory access continued

  44. A 98% hit rate: • effective access time is = (0.98 * 120) + (0.02 * 220) = 122 nsec • 22% slowdown in the memory access time

  45. 5.7. Multilevel Paging • In modern systems, the logical address space for a process is very large: • 232, 264 bytes • virtual memory allows it to be bigger than physical memory (explained later) • the page table becomes too large

  46. Example • Assume: • a 32 bit logical address space • page size is 4K bytes (212) • Logical address format: page number n page offset d 20 12 continued

  47. The page table must store 220 addresses (~ 1 million), each of size 32 bits (4 bytes) • 4 MB page table • too big • Solution: use a two-level paging scheme to make the page tables smaller.

  48. Two-level Paging Scheme • In essence: “page the page table” • divide the page table into two levels • Logical address format: • p1 = index into the outer page table • p2 = index into the page obtained from the outer page table p1 p2 page offset d page number

  49. Diagram memory page tables pg 0 Fig. 8.18, p.266 1 pg 1 : pages : 500 pg 100 : : pg 500 100 : :: : pg 708 708 : : pg 900 outer pagetable : 929 : pg 929 900 :

  50. Address Translation Fig. 8.19, p.267 logical address p1 p2 d p1 outer pagetable p2 d page table desired page

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