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Machine Access System Software Design and Documentation

Machine Access System Software Design and Documentation. Western Washington University By: Kevin Pogue. General System Design. Kinetis MK60DN512VMD10 Bus Frequency -100 MHz Memory Requirements 10 kB RAM 20 kB ROM Kernel Choice – MQX RTOS Tick Period – 1 ms. Priority of Tasks.

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Machine Access System Software Design and Documentation

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  1. Machine Access System Software Design and Documentation Western Washington University By: Kevin Pogue

  2. General System Design • Kinetis MK60DN512VMD10 • Bus Frequency -100 MHz • Memory Requirements • 10 kB RAM • 20 kB ROM • Kernel Choice – MQX RTOS • Tick Period – 1 ms

  3. Priority of Tasks 9) Start Task 10) RFID Task 11) Key Task 12) LCD Task 13) User Interface Task 14) Main Task

  4. Start Task • Initialize registers, hardware • Create tasks, control structures • Priority - 9 • Period: Once at startup • Estimated Execution Time: 200 ms • CPU Load: N/A

  5. RFID Task • Communicate with RFID hardware • Priority - 10 • Period – Sporadic > 1 s • Execution time – 100 ms • Task CPU load. • Peak - 0.1s / 1 s = 10% • Average – 0.1s / 300 s = 0.003%

  6. Key Task • Get and decode keypad input for use in the program • Priority - 11 • Period – 20 ms • Estimated Execution Time – 100 us • Task CPU load • Average - 100 us/20 ms = 0.5% • Peak – 500 us / 20 ms = 2.5%

  7. LCD Task • Display information to the user • Priority -12 • Sporadic > 50ms • Estimated Execution Time – 3.2 ms • Task CPU load • Peak (4 * 20 * 40 us ) / 50 ms = 6.4% • Average (4 * 20 * 40 us) / 1 s = 0.32%

  8. User Interface Task • Get input from and display information to user • Priority - 13 • Task Period – 30 ms • Estimated Task Execution Time - 1 ms • Task CPU load. • Peak – 1 ms/ 30 ms = 3.3% • Average – 1 ms / 30 ms = 3.3%

  9. Main Task Design • Control access decision making, output relay • Priority - 14 • Periodic – 500 ms • Estimated Task Execution Time – 50 us • Task/ISR CPU load • Peak – 500 us / 500 ms = 0.1 % • Average - 50 us / 500 ms = 0.01%

  10. CPU load L max= (0.1s) + (500 us) + (3.2ms) +(1 ms) + (500 us) (1s) ( 20 ms) (50ms) (30 ms) (500 ms) L max= 22.3% L average = 7.1%

  11. Modules

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