Technion – Israel Institute of Technology Department of Electrical Engineering

Written by: Haim Natan Benny Pano Supervisor: Gregory Mironov Technion – Israel Institute of Technology Department of Electrical Engineering High Speed Digital Systems Lab Inverse Matrix Accelerator Midterm Presentation Project no. D0623 Spring 2004

Project Goal Designing and implementing an FPGA circuitry that inverses a 625x625 matrix.

Inverter Matrix Inverted matrix Input & Output • Input: • * A 625x625 matrix Output: * A 625x625 inversed matrix

Project Requirements • The matrix will be of size 625x625 • Matrix elements will be of type 64 bits double precision floating point • The inverted matrix should be accurate as much as possible • Calculation time < 20ms

Interface • The matrices used will be on an on-board memory. • The FPGA will use the external memory as both the input and the output. • The project will be implemented on a Virtex II pro.

Project Background • A standalone system • Two algorithms were taken into account: a. Monte-Carlo based b. Linear inversing algorithm

N – number of markov chains T – length of each chain b – an inversed element MP() – a chain generator bi,j := 0; For c := 1 to N do { k0 := i ; w0 := 1 ; For t := 1 to T do { kt := MP( kt-1 ) ; wt := sign(dkt-1,kt) * wt-1 * Ekt-1 ; if kt = j then bi,j += wt ; } } bi,j /= N ; The Monte-Carlo algorithm (simplified version)

The MC algorithm (continued) • D = I – A • Ei =Σj|di,j| - weights vector • P is a transition probability matrix such that pi,j= |di,j| /Ei - used for generating the marcov chains.

The Linear Algorithm • A is the original matrix and B = I • Diagonalise A in order to transform it to an I matrix and do the exact same operations on matrix B to get the inverse of the original A.

The Linear Algorithm – C code for (i=0; i<n; i++) for (r=i; r<n; r++) { f = As[r][i]; for (c=0; c<n; c++) if (r==i) { As[r][c] /= f; Bs[r][c] /= f; } else { As[r][c] = As[r][c] / f - As[i][c]; Bs[r][c] = Bs[r][c] / f - Bs[i][c]; } }

C code - continued for (i=n-1; i>-1; i--) for (r=i-1; r>-1; r--) { f = As[r][i]; for (c=0; c<n; c++) Bs[r][c] = Bs[r][c] - f*Bs[i][c]; }

Comparing the algorithms

Conclusion The MC algorithm loses its advantages when large scale matrices are involved. In order to get accurate results, greater marcov chains are needed and implementation gets impractical on a single FPGA device. Also the need for 64bit FP type reduces the space available on the FPGA.

Memory Controller RAM Basic Block Diagram FPGA A Elements request Algorithm B Read/Write Elements transfer

T k = i MP MP MP E1 SW SW SW En SW SW SW 0 bi,j A A A Initial algorithm architecture

SW A Kin Tin Tin Ein Eout Win Wout * Kin Wint Rin Rout Cin Cout Kout Tout Vin Vout Switch & Accumulator Eout = Ein Rout = Rin Kout = Kin If Rin = Kin Then Tout = Ein Else Tout = Tin Cout = Cin Wout = Win * Tin Wint = Wout If Cin = Kin Then Vout = Vin + Wint Else Vout = Vin

Some scales • 64bit * 625 * 625 = 3MB • Two matrices needed  6MB • 20[msec] / (625^2) = 51.2 [nsec] per one matrix element  20Mhz • Considering an O(n^3) algorithm  12.2[Ghz]

Time schedule • 01/06/2004 – Algorithm Architecture study • 08/06/2004 – Memory controller unit designing. • 15/06/2004- Start of code writing and finish of the FP code. • 01/07/2004 – Start of VHDL simulation using the written c program.

Time schedule – cont. • 08/07/2004 – Start of VHDL debug and first chip burning. • 26/07/2004 – Final report and Project presentation

Technion – Israel Institute of Technology Department of Electrical Engineering