ME 4447/6405

1. ME 4447/6405 Microprocessor Control of Manufacturing Systems and Introduction to Mechatronics Instructor: Professor Charles Ume Interrupts and Resets

2. You might want instructions executed immediately after internal request and/or request from peripheral devices when certain condition are met . Interrupt provides way to temporarily suspend current program execution in order to execute certain set of tasks. Reason for Interrupts

3. There are two methods of checking when requests are made internally or from peripheral devices. Polling Interrupts Methods of Checking for Requests

4. An iterative approach which constantly checks devices for data Inefficient method for checking when input data has come in because no other instructions can be executed during polling process Polling

5. Interrupts Communication between CPU and I/O devices can be established with issue of interrupt request NOTE: Request can be issued at any time CPU suspends execution of main program until instructions in Interrupt Service Routine (ISR) are completely executed Returns to main program after ISR is completed

6. There are two types of interrupts. Maskable Non-Maskable Types of Interrupts

7. 27 Maskable Interrupts Two types of Masking Local Interrupt enable bit Global I-bit in CCR Follows a default priority arrangement Any one interrupt can be promoted to higher priority using HPRIO register Maskable Interrupts • IRQ • Real-Time Interrupt • Standard Timer Channel 0 • Standard Timer Channel 1 • Standard Timer Channel 2 • Standard Timer Channel 3 • Standard Timer Channel 4 • Standard Timer Channel 5 • Standard Timer Channel 6 • Standard Timer Channel 7 • Standard Timer Overflow • Pulse Accumulator A Overflow • Pulse Accumulator Input Edge • SPI transfer Complete • SCI system • ATD • Port J • CRG PLL Lock • CRG Self Clock Mode • Flash • CAN Wakeup • CAN Errors • CAN Receive • CAN Transmit • Port P • PWM Emergency Shutdown • VREG LVI

8. IRQ pin provides additional external interrupting source IRQE bit in Options Register used to configure IRQ for Edge-Sensitive-Only Operation IRQE = 0  IRQ is configured for low level sensitive operation IRQE = 1  IRQ is configured for falling edge-sensitive operation Maskable Interrupts: IRQ Input

9. Interrupts from Internal Peripheral Subsystems Flag bit, which is set after action takes place Interrupt enable bit, which enables flag to generate interrupt service Maskable Interrupts: Peripheral Subsystems

10. Maskable Interrupts Priority IRQ Real-Time Interrupt Standard Timer Channel 0 Standard Timer Channel 1 Standard Timer Channel 2 Standard Timer Channel 3 Standard Timer Channel 4 Standard Timer Channel 5 Standard Timer Channel 6 Standard Timer Channel 7 Standard Timer Overflow Pulse Accumulator A Overflow Pulse Accumulator Input Edge SPI transfer Complete SCI system ATD Port J CRG PLL Lock CRG Self Clock Mode Flash CAN Wakeup CAN Errors CAN Receive CAN Transmit Port P PWM Emergency Shutdown VREG LVI Interrupt Priority: Maskable Any can be assigned the highest maskable interrupt priority...

11. Used to elevate priority of any one maskable interrupt Default is IRQ Set by changing contents of HPRIO (Highest Priority Interrupt Register) Can only be written when I-bit is set HPRIO Register for Maskable Interrupts

12. HPRIO Register for Maskable Interrupts Address: $001F • PSEL[7:1] – Priority Select Bits • Selects one interrupts source to be elevated • Can only be written while I-bit in the CCR is set • Write the low byte of the maskable interrupt vector to HPRIO to elevate that maskable interrupt to the highest priority • Ex: writing $DE to HPRIO elevates the Standard Timer Overflow to highest priority (Standard Timer Overflow vector = $FFDE)

13. 6 Non-Maskable Interrupts Follows a default priority arrangement Interrupts are not subject to global masking Non-Maskable Interrupts POR of RESET pin Clock monitor reset COP watchdog reset Unimplemented instruction trap Software interrupt (SWI) XIRQ interrupt

14. Generates interrupt request to Unimplemented instruction trap vector Reinitializes stack pointer once interrupt service is completed Left un-initialized, illegal opcode vector can cause infinite loop causing stack underflow Non-Maskable Interrupts:Unimplemented instruction trap

15. Software instruction, thus cannot be interrupted until completed Uninhibited by global mask bits in the CCR Similar to other interrupts, sets I-bit upon servicing Non-Maskable Interrupts: Software Interrupt

16. Enabled by TAP instruction by clearing X-bit upon system initialization After being cleared, software cannot set X-bit, thus XIRQ is non-maskable Higher priority than any source maskable by I-bit Both X and I bits are automatically set by Reset or recognition of XIRQ interrupt RTI restores X and I bit to pre-interrupt states Non-Maskable Interrupts: XIRQ

17. Stacking Order when an Interrupt Occurs Last value to be pulled from stack

18. Each type of interrupt has associated vector addresses Vector addresses change depending on whether MON12 is in use With MON12 in use, user must use Monitor Interrupt Vector Table Interrupt Vectors

19. In this case you must write the address of your Interrupt Service Routine to the vector address found in the Monitor Interrupt Vector Table MON12 in Use

20. Interrupt Vector Table: MON12 in Use … …

21. Interrupt vector addresses are usually occupied by MON12 With MON12 not in use, starting ISR address must be programmed in standard vector address MON12 Not in Use

22. Interrupt Vector Table: MON12 not in Use

24. Interrupt Flow Interrupt condition is met A B Global Masking YES Analyze Priority ISR instruction NO Set (I) or (X) to prohibit another Interrupt RTI NO Local Masking YES YES NO Clear I or X bit in CCR Complete Current Instruction Standard Interrupt Table Restore Registers w/ org. Values Store all registers on the Stack Load Address in appropriate vector Note: Local mask must be cleared prior to performing RTI Continue Program A B

25. Elapsed Time Example Write a routine to interrupt the MC9S12C32 after 10 msec of elapsed time (Assume E= 1 Mhz, Prescaler = 1, MON12 in use) ORG $1000 LDD #$FFFF /*Delays any TC3 compares*/ STD TC3H /*Set output compare to the longest time so that you would not have output compare occurring when you are initializing*/ OR SEI /*Set I-bit to prevent interrupt service during set-up*/ LDAA #BIT3HI /* BIT5HI = %0010000*/ STAA TIOS /* Select TC3 as an output compare*/ STAA TFLG1 /* Clear TC3 Interrupt Flag*/ STAA TIE /* Enable TC3 Interrupt */ LDAB #$C0 STAB TCTL2 /* PT3 will be high for a successful compare */ LDX #TC3ISR /* TC3ISR = $2000, 2 bytes- beginning address of interrupt service routine*/ STX TC3VEC /* TC3VEC= $0FE8, This will cause the high byte ($20) of the service routine address to be stored in location $0FE8 and the low byte ($00) to be stored in $0FE9 */ LDD TCNT /* TCNT=$0044 */ ADDD #DLYIOMS /* DLYIOMS = $2710 = 10000 */ STD TC3 /* IF not done elsewhere */ CLI /* Clear I bit */

26. Elapsed Time Example Write a routine to interrupt the MC9S12C32 after 10 msec of elapsed time (Assume E= 1 Mhz, Prescaler = 1, MON12 in use) ORG $1000 LDD #$FFFF /*Delays any TC3 compares*/ STD TC3H /*Set output compare to the longest time so that you would not have output compare occurring when you are initializing*/ OR SEI /*Set I-bit to prevent interrupt service during set-up*/ LDAA #BIT3HI /* BIT3HI = %0003000*/ STAA TIOS /* Select TC3 as an output compare*/ STAA TFLG1 /* Clear TC3 Interrupt Flag*/ STAA TIE /* Enable TC3 Interrupt */ LDAB #$C0 STAB TCTL2 /* PT3 will be high for a successful compare */ LDD TCNT /* TCNT=$0044 */ ADDD #DLYIOMS /* DLYIOMS = $2710 = 10000 */ STD TC3 /* IF not done elsewhere */ CLI /* Clear I bit */ …. SWI END ORG $0FE8 FDB TC3ISR

27. TFLG2 EQU $004F *Timer Interrupt Flag 2 TSCR2 EQU $1024 *Timer Interrupt Mask 2 TOFISR EQU $1500 *ISR memory location PROGRAM EQU $1000 STRING EQU $2000 OUTSTRG EQU $FF5E VECTOR EQU $0FDE ORG STRING FCC 'TICK' FCB $04 ORG PROGRAM *Set I-bit to prevent interrupt service during set-up SEI Start timer, turn on TEN LDAA #$80 STAA TSCR2 *TOF Interrupt Enabled STAA TFLG2 *Clears TOF Interrupt Flag LDX #TOVISR *Loads register X with #1500 *Stores content of register X to address Vector incremented STX VECTOR CLR $0001 CLI * Clears I-bit to allow servicing of interrupt LOOP BRA LOOP SWI *Software Interrupt End ORG TOVISR LDAA $0001 * Loads address $0001 content INCA *Increment by 1 STAA $0001 *Stores value back to address CMPA #30 *Compares value to decimal 30 BNE A1 *Loads index register X with content of STRING LDX #STRING JSR OUTSTRG CLR $0001 *Clear address A1 LDAA #$80 *Loads binary 10000000 STAA TFLG2 *Clears local flag RTI Example: Timer Overflow Interrupt Pre-interrupt service set-up

28. Forces the MCU to: assume set of initial conditions begin executing instructions at predetermined starting address. Resets

29. Like interrupts, resets share concept of vector fetching to force new starting point for further CPU operations. In contrast to interrupts, resets stop completely execution of set of instructions. As well, they always rest MCU hardware. Resets

30. Power on Reset (POR) External Reset (RESET) Computer Operating Properly (COP) Reset Clock Monitor Reset Sources of Resets

31. Power-On Reset (POR) Used only for power-up conditions to initialize MCU internal circuits. Applying Vdd to MCU triggers POR circuit, initiates reset sequence, and starts internal timing circuit. 4064 clock cycle delay after oscillator becomes active, allows clock generator to stabilize. Power-On Resets

32. System reset can also be forced by applying low level to RESET pin. External source must hold pin low for more than 4 cycles. If this happens, pin is further sampled 2 cycles after Low level at sampling instant indicates that reset has been caused by external device. External Reset

33. Protects against software failures When enabled, software to keep free- running watchdog timer from timing out is activated System reset is initiated when software stops executing in the intended sequence Computer Operating Properly Reset

34. COP is enabled or disabled by setting NOCOP bit in CONFIG register. To change status of COP system, contents of CONFIG register are changed and system reset is initiated. COP timer rate is controlled in OPTION Register. The system E-clock is divided by 2^15 and further scaled by 1, 2 and 4. COP Reset continued

35. Clock Monitor Reset circuit is based on internal resistor capacitor time delay. If no MCU clock edges are detected within this RC time delay, clock monitor, if set by CME control bit, would generate system reset. Clock Monitor Reset

36. MPU senses whether reset pin rises to logic 1 within two E-clock cycles after internal device releases reset. When reset condition is sensed, RESET pin is driven low by internal device for 4 E-clock cycles, then released. Two E-clock cycles later, it is sampled. If pin is still held low, CPU assumes that external reset has occurred. If pin is high, it indicates that reset was internally initiated. How the MPU Distinguishes between Internal and External Resets

37. CPU Memory Map Timer Real-time Interrupt Pulse Accumulator SPI ADC System COP SCI Occurrence of Reset Affects

38. When Reset is triggered Vector fetch (Program counter loaded with contents of specified address) S, X and I bits set in CCR MCU hardware reset Checks for interrupts Process Flow out of Resets

39. Suspends CPU operation until reset or interrupt occurs Used to reduce power consumption Two standby modes: WAIT STOP Standby Modes

40. Opcode (WAI) Suspends CPU processing CPU registers are stacked On-chip crystal oscillator remains active Exit WAIT mode through external IRQ, XIRQ, or any internally generated interrupts Standby Modes: WAIT

41. If S-bit in the CCR is 0, CPU goes into stop mode Else, opcode is treated as NOP All clocks stopped  internal peripherals stopped Retains data in Internal RAM if VDD is maintained CPU state and I/O pin levels are static Exit STOP mode through external interrupts, pending edge-triggered IRQ or RESET pin Standby Modes: STOP

42. Recovering through XIRQ X-bit is clear  Returns to stacking sequence leading to normal XIRQ request X-bit is set  Returns to instruction immediately following STOP instruction Standby Modes: STOP

43. Questions???