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This project involves implementing edge detection algorithms in hardware using FPGA for high-speed image processing. It utilizes a CMOS color camera module to provide RGB pixel data, with outputs for Direct video, Edges, and possibly posterization. The system includes an LCD screen and a PSP screen to display 24-bit data signals at 480x272 resolution. Key components are an EP3C16E144C8N FPGA, offering 84 I/O pins and 15,408 logic elements. The project focuses on optimizing 2D convolution computations for efficient image filtering.
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EEL4924 Senior Design Date: 02 March 2011 DIF – Digital Imaging Fast Ali Nuhi and Everett Salley
Project Description • Image Processing using an FPGA • Implementing edge detection algorithms in hardware • Actual application for all the theory learned in Signal Processing Courses • Would need a high speed DSP to achieve the same effect • User defined outputs • Direct video, Edges, possibly posterization
LCD Screen • LQ043T3DX02 – PSP Screen • 24bit data signals (8bit*RGB) • 9MHz clock • 480x272x3 • Cheap, well documented
Camera • TCM8230MD – CMOS Color Camera • Meets VGA format requirments • Camera module will be responsible for providing RGB pixel data • 25Mhz clock, 30fps max • Outputs RGB 5:6:5 • 8bits at a time
FPGA • EP3C16E144C8N – 144PIN EQFP • 84 I/O Pins (also a 160 I/O version) • 15,408 Logic Elements • 516,096 RAM Bits • 112 9bit multipliers • Crossing Clock Domains • Camera, LCD, Memory
2D Convolution Data • Common operation in many 2D filters Kernel Result
Convolution in hardware • You don’t need to know the entire image, only the local pixels • For a 3x3 kernal, the result of 2D convolution is the sum of 9 multiplies. • Ex) Sobel Edge detection requires two 3x3 convolutions (as well as a few other operations)
