CSCE 212 Chapter 5 The Processor: Datapath and Control

1. CSCE 212Chapter 5The Processor: Datapath and Control Instructor: Jason D. Bakos

2. Goal • Design a CPU that implements the following instructions: • lw, sw • add, sub, and, or, slt • beq, j

3. Datapath

4. Instruction Fetch Datapaths

5. Register File and ALU

6. BEQ Datapath

7. Load, Store, and R-type Datapath

8. Combined Datapaths

9. ALU Control • ALU performs function based on 4-bit ALU_operation input • Add a lookup table that instructs ALU to perform: • add (for LW, SW), or • subtract (for BEQ), or • perform operation as dictated by R-type function code

10. MIPS Datapath

11. MIPS Datapath with Control

12. MIPS Datapath with Jump

13. Single-Cycle • This is a single-cycle implementation • Each instruction is executed within one clock cycle • Must be set for worst-case delay (LW)

14. Multicycle Implementation • Break instruction execution into a sequence of steps • Adjust cycle time to be long enough to perform one basic operation • fetch, register read, ALU, memory access, register write • Must add registers to carry computed values from one cycle to next • Still can perform independent operations in parallel, i.e.: • fetch instruction and compute next PC address • read registers and compute branch address • Allows us to re-use ALU

15. Multicycle MIPS Implementation

16. Multicycle Control • Instruction fetch • Information available: PC • Performed for all instructions • RTL: • IR <= Memory[PC]; • PC <= PC + 4; • Instruction decode and register fetch • Information available: PC, instruction • Performed for all instructions • RTL: • A <= Reg[IR[25:21]]; • B <= Reg[IR[20:16]]; • ALUOut <= PC + (sign-extend(IR[15:0]) << 2);

17. Multicycle Control • Execution, memory address computation, or branch completion • Information available: PC, instruction, (rs), (rt), (ALUOut) • Memory reference: • ALUOut <= A + sign-extend(IR[15:0]); • Arithmetic-logical instruction (R-type): • ALUOut <= A op B; • Branch: • if (A == B) PC <= ALUOut; • Jump: • PC <= {PC[31:28], IR[25:0], “00”};

18. Multicycle Control • Memory access or R-type completion step • Information available: PC, instruction, (rs), (rt), (ALUOut) • Load: • MDR <= Memory[ALUOut]; • Store: • Memory[ALUOut] <= B; • Arithmetic-logical instruction (R-type): • Reg[IR[15:11]] <= ALUOut;

19. Multicycle Control • Memory read completion step • Information available: PC, instruction, (rs), (rt), (ALUOut), (MDR) • Load: • Reg[IR[20:16]] <= MDR;

20. Multicycle Control

21. Adding Datapaths and Control • How to add these instructions: • addi rt, rs, imm • bgtz rs, target • bgtzal rs, target

22. Exceptions and Interrupts • Events other than branches or jumps that change the normal flow of instruction execution • Examples: • I/O device request (external, interrupt) • System call (internal, exception) • Arithmetic overflow (internal, exception) • Invalid instruction (internal, exception) • Hardware malfunction (internal or external, exception or interrupt)

23. Interrupts and Exceptions • What to do? • Execute code in response to event (handler) • Save PC (EPC reg,) • Record cause (Cause reg.) • Set new PC (4) • Return from handler • Restore PC • Enable e/i (shift Status reg.) • Determining type of exception • Use vectored exceptions • Infer type from address • Use polled exceptions • Use Cause register • This is what MIPS does

24. Example Implementation • Example: • Use polled approach • All exceptions and interrupts jump to single handler at address 8000 0180 • The cause is recorded in the cause register • The address of affected instruction is stored in EPC

25. Example Implementation

26. Example Implementation