Eri Prasetyo Wibowo Universitas Gunadarma eri.staffsite.gunadarma.ac.id

1. System On Chips ( SOCs) Eri Prasetyo Wibowo Universitas Gunadarma http://eri.staffsite.gunadarma.ac.id http://pusatstudi.gunadarma.ac.id/pscitra

2. DIFINISI System-on-a-chip or system on chip (SoC or SOC) refers to integrating all components of a computer or other electronicsystem into a single integrated circuit (chip). It may contain digital, analog, mixed-signal, and often radio-frequency functions – all on one chip. A typical application is in the area of embedded systems. ( wikipedia) System-on-a-chip (SoC) technology is the packaging of all the necessary electronic circuits and parts for a "system" (such as a cell phone or digital camera) on a single integrated circuit ( IC ), generally known as a microchip. For example, a system-on-a-chip for a sound-detecting device might include an audio receiver, an analog-to-digital converter ( ADC ), a microprocessor , necessary memory , and the input/output logic control for a user - all on a single microchip.

3. IC Shrinks CPU Base Design SoC ADC CPU FPGA Or Keep Package Same Size RAM EEPROM MOORE’S LAW:2X FUNCTIONALITY EVERY 18 MONTHS CPU

4. DESIGN PRODUCTIVITY LAGS MANUFACTURING CAPABILITY Maya Rubeiz USAF Wright Labs maya.rubeiz@sn.wpafb.af.mil http://rassp.scra.org

5. HW-SW Kernel + Reference Design Pre-Qualified/Verified Foundation-IP* Scaleable bus, test, power, IO, clock, timing architectures MEM Application Space Hardware IP Processor(s), RTOS(es) and SW architecture CPU FPGA SW IP Reconfigurable Hardware Region (FPGA, LPGA, …) Programmable *IP can be hardware (digital or analogue) or software. IP can be hard, soft or ‘firm’ (HW), source or object (SW) Foundry-Specific HW Qualification SW architecture characterisation SOC PLATFORM DESIGN gmartin@cadence.com

6. FPGAs can contain soft or hard IP (including CPUs). www.atmel.com www.altera.com www.triscend.com www.xilinx.com RECONFIGURABLE FPGA-BASED BOARDS CAN PROTOTYPE DIGITAL DESIGNS

7. APPLICATION REQUIREMENTS TEAM PROJECT HDL HDL HDL HDL DESIGN FOR REUSE FPGA FPGA FPGA FPGA VERIFICATION DESIGN WITH REUSE SYSTEM INTEGRATION SoC DESIGN-FOR-REUSE and DESIGN-WITH-REUSE

8. High performance ASICs can now contain programmable logic (embedded FPGA tiles) as needed for flexibility. ARM SOC WITH RECONFIGURABLE COMPONENTS www.lsil.com www.adaptivesilicon.com

9. A matrix of configurable analog opamps and interconnect can be used to perform filtering and other signal conditioning operations. CONFIGURABLE ANALOG ARRAYS www.anadigm.com www.latticesemi.com

10. Conventional Transistor Layout Radiation-Tolerant Layout S G D S D G Radiation Effects REF: cern.ch Current (Drain) Desired Behavior Voltage (Gate) RADIATION-TOLERANT CIRCUITS CAN BE MADE USING CONVENTIONAL PROCESSES

11. SHARING MULTI-PROJECT MASKS AND WAFERS SAVES MONEY Single-User Wafer Shared, Multi-Project Wafer www.mosis.org

12. MULTI-PROJECT SERVICES PROVIDE ACCESS TO STATE-OF-THE-ART COMMERCIAL PROCESSES

13. TSMC 0.35µ TSMC 0.25µ 5-metal, 2-poly TSMC 0.18µ 6-metal 2.5/3.3v I/O, 1.5/1./8v Core Peregrine SOI-SOS 0.50µ TSMC 0.15µ TSMC 0.13µ 6-metal, 1 poly, silicided, Cu IBM SiGe 0.5µ IBM SiGe 0.25µ PROCESSES AVAILABLE VIA MOSIS NOW NEXT 6 MONTHS www.mosis.org

14. Assemble individual components using a board with reconfigurable interconnect to finalize the system specs. Model the entire system and simulate at a high level. • Design and prototype an analog I.C. via MOSIS or CMP. • Design and prototype the digital components using FPGAs. SoC • Integrate the analog and digital sections into a single SoC. STEPS IN MIXED-SIGNAL SOC DEVELOPMENT

15. BAGAIMANA MEMULAI DESAIN DALAM SOCs