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The PHENIX Muon Identifier Front End Electronics

The PHENIX Muon Identifier Front End Electronics. Andrew Glenn (University of Tennessee), for the PHENIX collaboration. April APS Meeting in Washington, D.C. Andrew Glenn 5/1/01. The Experiment. South. North. Andrew Glenn 5/1/01. The Muon Identifier. MuID. 6340 Tubes per arm.

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The PHENIX Muon Identifier Front End Electronics

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  1. The PHENIX Muon Identifier Front End Electronics Andrew Glenn (University of Tennessee), for the PHENIX collaboration April APS Meeting in Washington, D.C. Andrew Glenn 5/1/01

  2. The Experiment South North Andrew Glenn 5/1/01

  3. The Muon Identifier MuID 6340 Tubes per arm 3170 Active Channels MuTr Andrew Glenn 5/1/01

  4. The MuID Main Functions • Distinguish muons from other particles, primarily pions • m p separation of ~3*10-3 • Provide triggering capability • Large groupings of ORed tubes from lemo pseudo-trigger outputs for commissioning, cosmic-ray trigger, and possible fallback. • Optical fiber outputs for full tracking trigger. (J. Newby V10.008) Andrew Glenn 5/1/01

  5. The Muid FEE Main Components • In-panel Amplifier/HV Distribution Boards • Readout Cards (ROCs) • Front End Module Cards (FEMs) • Transition Cards, Backplanes, Crates Basic Data Flow For 1 Orientation In-panel Amplifiers Optical Fiber ROCs (20) LVL1 trigger Twisted-paircables Transition Cards (20) DigitalSignals(Hits) Analog signals DataAcquisitionSystem FEM (1) Optical Fiber DigitalBackplane Andrew Glenn 5/1/01

  6. In-panel Amplifier/HV Boards • Produce Differential Output of ~± 250mV • Push Analog Signals Over ~30 meter Twisted-pair Cable • Must Stand the Test of Time • Polyfuses • Double-diode protection against broken wire • Diode clamps prevent reverse-bias Andrew Glenn 5/1/01

  7. MuID FEE Diagram Digital Backplane Data, serial data, control and power Six sets of 16 twisted-pair inputs from MuID panels 16 16 16 16 16 16 96 Channels Transition Card FEM ROC Data Formatting Serial Control Timing & Control, eg. Mode bits, LVL1, BCLK (20 per Crate) Signal Conditioning -Digitization -Variable Delay Buffering -LVL1 Latency -“Alive for 5” 96 bits out to LVL1 G-link @6xBCLK G-link from GTM G-link to DCM ARCNet in Andrew Glenn 5/1/01

  8. MuID ROC Diagram FIFO cntrl 16 16 Receiver & Threshold Delay & Latch FPGAs (6) And Clock delay chips (12) Data Store FIFOs (3) Five Event FIFO FPGA 16 32 Analog data Data 16 16 P1 LVL1_Acpt 16 16 32 /RD 96 16 16 32 Analog data /RD_EN 16 16 P2 /DV 16 16 sdin, rdbak, slatch, sclk, sdout, sreset Pulser lines 96 6 96 BCLK /HALT Analog Spy Output Align bit Analog Muxes (7) 96 LVL1_Acpt Serial String & Pulser 28 BCLK Board Resets (4) /RD Align bit Digital Spy Output /DV FPGA Prog. Trigger Format FPGA Trigger Data 6 Data (16) P3 6X BCLK Mode CLK 5 20 Address Decode PLD Xfer Mode (2) /RD_EN MP_dat (2) Trigger GLink (60 MHz) Greset /ALE TTL Glink Circuit ED FEM Device Addr (5) Locked ARCNet Addr/Data (5) Geographic Addr (6) Andrew Glenn 5/1/01

  9. MuID FEM Diagram Strobe, /CAV, /DAV 16 ROC Data Data Formatter Data (16) 5 FEM Addr FIFO WR Clk & EN (2) /ALE /RD RD Clk & EN (2) GLink XMIT Glink To DCM /ROC_DV CommandLines (7) Glink From T&C /HALT Mode Control LVL1 Acpt Glink RCV Mode Bits (20) LVL1 accept BCLK 4xBCLK EnDat0 User Bit [2:0] Mode Bits [7:0] Mode Enable BCLK Resets (4) Align bit FPGAProgram (6) FPGA Data (16) Address &RD Cntrl (7) Rx ResetStat0 5 ARCNet Subsystem ARC Addr/Data Mode CLK Data Formatter Diagnostic FPGA Address Decode PLD Xfer Mode (2) Serial Data (6) MP_dat (2) ARC bus (10) ARCNet Serial line FPGA Program (6) GeographicAddress (6) 6 Andrew Glenn 5/1/01

  10. Other Components Transition Card Passthrough backplane Crate Digital Backplane 2 Crates per rack: 1 for horizontal tubes and 1 for vertical Andrew Glenn 5/1/01

  11. MuID FEE Photos Pseudo-trigger outputs To Trigger FEM FEM Signal Wires Andrew Glenn 5/1/01

  12. Communication Overview • Slow Controls (Timing Delays, Thresholds …) • Serial Downloads via ARCNet to FEM • Timing and Modebits from Granule Timing Module (GTM) • Fiber Optic G-Link (On FEM) • Formatted Data to Data Collection Module (DCM) • Fiber Optic G-Link (On FEM) • Level1 Trigger • Lemo Cable Pseudo-trigger outputs (commissioning) • 6x Fiber Optic G-Link (Full Tracking Trigger) Andrew Glenn 5/1/01

  13. ARCNet GUIs Java based GUIs set various parameters over ARCNet via a CORBA server. Three Types of Downloads: -DMUX (Shown) -DAC -Miscellaneous Andrew Glenn 5/1/01

  14. Current FEE Status • Successful basic commissioning run last year. (H. Sato V10.006) • All FEMs have passed quality assurance tests. • All ROCs have passed quality assurance tests. • Noise and trigger studies at an advanced stage. • Data in ~1 Month! Please seehttp://phenix.bnl.gov/WWW/muon/muid_fee/for additional information. Andrew Glenn 5/1/01

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