Introduction toVLSI Programming Lecture 4: Data handshake circuits

1. Introduction toVLSI Programming Lecture 4: Data handshake circuits (course 2IN30) Prof. dr. ir.Kees van Berkel Dr. Johan Lukkien

2. Time table 2005 Kees van Berkel

3. Lecture 4 Outline: • Recapitulation Lecture 3 • Data encoding; push and pull handshakes • Tangram assignment command • Handshake components: handshake latch, transferrer, multiplexer, adder • Handshake circuits & Tangram programs: fifo buffers and shift registers Kees van Berkel

4. Header: handshake circuit L=0 L=1 Kees van Berkel

5. ck ak ar br x cr bk Sequencer realization Sequencer: area, delay, energy: • Area: 5 gate equivalents • Delay per cycle: 8 gate delays • Energy per cycle: 10 transitions Kees van Berkel

6. requestar active side passive side acknowledge ak data ad active side passive side acknowledgeak dataad Handshake signaling and data push channel versus pull channel requestar Kees van Berkel

7. time Handshake signaling: push channel req ar ack ak earlyad broad ad late ad Kees van Berkel

8. Data bundling In order to maintain event ordering at both sides of a channel,the circuit must satisfy data bundling constraint: • for push channel: delay along request wire must exceed delay of data wire; • for pull channel: delay along acknowledge wire must exceed delay of data wire. Kees van Berkel

9. time Handshake signaling: pull channel When data wires are invalid: multiple and incomplete transitions allowed. req ar ack ak earlyad broad ad late ad Kees van Berkel

10.  y   | x f  yw y y z f f   xw0 zw z z | x xr xw1 | x Tangram assignment x:= f(y,z) Handshake circuit Kees van Berkel

11.  time  b c Four-phase data transfer r / br ba / cr ca / a bd / cd 1 2 3 4 5 Kees van Berkel

12. w x r wd rd wr Handshake latch [ [ w ; [w : rd:= wd] [] r ; r] ] • 1-bit handshake latch: wd  wr  rd  wd  wr  rd wk = wr rk = rr Kees van Berkel

13. wr rr wd1 rd1 wd2 rd2 ... wdN rdN wk rk N-bit handshake latch area, delay, energy • area: 2(N+1) gate eqs. • delay per cycle: 4 gate delays • energy per write cycle: 4 + 0.5*2N transitions, in average Kees van Berkel

14. a  b c ar ak ck br cr bk cd bd Transferrer [ [ a : (b ; c)] ; [ a : (b ; cd:= bd ; c ; cd:= )] ] Kees van Berkel

15. a c | b Multiplexer [ [ a : c ; a : (cd:= ad; c ; cd:= )[] b : c ; b : (cd:= bd; c ; cd:= )] ] Restriction: arbr must hold at all times! Kees van Berkel

16. Multiplexer realization control circuit data circuit Kees van Berkel

17. b f a c Logic/arithmetic operator [ [ a : (b || c) ]; [ a : ((b || c) ; ad:= f(bd , cd ))]] Cheaper realization (delay sensitive): [ [ a : (b || c) ]; [ a : ((b || c) ; ad:= f(bd , cd ))]; “delay” ; ad:= ] Kees van Berkel

18. a b BUF1 A one-place fifo buffer byte = type [0..255] & BUF1 = main proc(a?chan byte & b!chan byte).beginx: var byte|forever do a?x ; b!x odend Kees van Berkel

19. ;  a x x  b   ;  ; a   x  b  A one-place fifo buffer byte = type [0..255] & BUF1 = main proc(a?chan byte & b!chan byte).begin x: var byte|forever do a?x ; b!x odend  a x x b Kees van Berkel

20. BUF1 b BUF1 a c 2-place buffer byte = type [0..255] &BUF1 = proc (a?chan byte & b!chan byte).begin x: var byte |forever do a?x ; b!x od end &BUF2: main proc (a?chan byte & c!chan byte).begin b: chan byte |BUF1(a,b) || BUF1(b,c)end Kees van Berkel

21. Two-place ripple buffer Kees van Berkel

22.  a b Two-place wagging buffer byte = type [0..255]&wag2: main proc(a?chan byte & b!chan byte).begin x,y: var byte|a?x ; forever do (a?y || b!x) ; (a?x || b!y)odend Kees van Berkel

23. Two-place ripple register …begin x0, x1: var byte|forever do b!x1 ; x1:=x0; a?x0 odend Kees van Berkel

24. 4-place ripple register byte = type [0..255]&rip4: main proc (a?chan byte & b!chan byte).begin x0, x1, x2, x3: var byte|forever do b!x3 ; x3:=x2 ; x2:=x1 ; x1:=x0 ; a?x0 odend Kees van Berkel

25. x1 x2 x3 x2 x3 x3 x0 x1 x0 x0 x0 x1 x2 x3 4-place ripple register • area : N (Avar + Aseq ) • cycle time : Tc = (N+1) T:= • cycle energy: Ec = N E:= Kees van Berkel

26. Introducing vacancies …begin x0, x1, x2, x3, v: var byte|forever do (b!x3 ; x3:=x2 ; x2:=v) || (v:=x1 ; x1:=x0 ; a?x0) odend • what is wrong? Kees van Berkel

27. Introducing vacancies forever do ((b!x3 ; x3:=x2) || (v:=x1 ; x1:=x0 ; a?x0)) ; x2:=v od or: forever do ((b!x3 ; x3:=x2) || (v:=x1 ; x1:=x0));(x2:=v || a?x0)od Kees van Berkel

28. m0 m0 m1 m1 m2 m2 m3 m3 x0 x0 b b s0 s0 s1 s1 s2 s2 m3 x0 b m0 m1 m2 m0 m0 m1 m1 m2 m2 m3 m3 x0 x0 b b s0 s1 s2 s0 s0 s1 s1 s2 s2 “synchronous” 4-p ripple register forever do (s0:=m0 || s1:=m1 || s2:=m2 || b!m3 ); ( a?m0 || m1:=s0 || m2:=s1 || m3:=s2)od Kees van Berkel

29. x0 x1 x0 x1 y0 y1 a a a a x2 b b b b y0 y1 x0 x1 a b y0 x2 y1 x3 4-place wagging register forever do b!x1 ; x1:=x0 ; a?x0; b!y1 ; y1:=y0 ; a?y0od Kees van Berkel

30. 8-place register 4-way wagging forever do b!u1 ; u1:=u0 ; a?u0; b!v1 ; v1:=v0 ; a?v0; b!x1 ; x1:=x0 ; a?x0; b!y1 ; y1:=y0 ; a?y0od Kees van Berkel

31. Four 88 shift registers compared Kees van Berkel

32. Next session: lecture 5 Outline: • Tangram overview • Compilation: Tangram Handshake Circuits • Tools • Demonstration • Lab work: assignment “fifos and registers” Kees van Berkel