1 / 13

Architectures for Baseband Processing in Future Wireless Base-Station Receivers

Architectures for Baseband Processing in Future Wireless Base-Station Receivers. Sridhar Rajagopal ECE Department Rice University March 22,2000. This work is supported by Nokia, Texas Instruments, Texas Advanced Technology Program and NSF. Third Generation Wireless. First Generation

naida-koch
Download Presentation

Architectures for Baseband Processing in Future Wireless Base-Station Receivers

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Architectures for Baseband Processing in Future Wireless Base-Station Receivers Sridhar Rajagopal ECE Department Rice University March 22,2000 This work is supported by Nokia, Texas Instruments, Texas Advanced Technology Program and NSF

  2. Third Generation Wireless First Generation Voice Eg: AMPS Second/Current Generation Voice + Low-rate Data (9.6Kbps) Eg : IS-95(N-CDMA) Third Generation + Voice + High-rate Data (2 Mbps) + Multimedia W-CDMA CAIN Project

  3. Noise +MAI Base Station Reflected Paths Direct Path User 1 User 2 Main Parts of Base-Station Receiver • Channel Estimation • Noise, MAI • Attenuation • Fading • Detection • Detect user’s information • Multiple Users • Decoding • Coding/Decoding improve error rate Performance • Coding done at handset Wireless Communication Uplink CAIN Project

  4. User Interface Translation Synchronization Transport Network Physical Layer OSI Antenna Layers 3-7 Multiuser Detector Data Decoder Demux Data Link Layer (Converts Frames to Bits) OSI Layer Estimated Amplitudes & Delays 2 Pilot Channel Estimator Physical Layer (hardware; raw bit stream) OSI Layer 1 Base-Station Receiver CAIN Project

  5. 5 x 10 Data Rates for a typical DSP Implementation 2 Data Rates 1.5 Data Rate Requirement = 128 Kbps 1 0.5 0 9 10 11 12 13 14 15 Number of Users Need for Better Architectures • Current DSPs need orders of magnitude improvement to meet real-time requirements. • Reason • Sophisticated Algorithms, Computationally Intensive Operations • Floating Point Accuracy • Solution • Try sub-optimal/iterative schemes • Fixed Point Implementation • Use structure in the algorithms • Parallelism / Pipelining • Task Partitioning • Bit Level Arithmetic CAIN Project

  6. Channel Estimation - An example • Channel Estimation† includes • Matrix Correlations, Matrix Inversions, Multiplications • Floating Point Accuracy • Need to wait till all bits are received. • Modified Channel Estimation Algorithm • Matrix Inversion eliminated by Iterative Scheme • Based on Gradient / Method of Steepest Descent • Negligible effect on Bit error Performance • Fixed Point accuracy, Computation spread over incoming bits • Features to support Tracking over Fading Channels easily added. †Maximum Likelihood Based Channel Estimation [C.Sengupta et al. : PIMRC’1998, WCNC’1999] CAIN Project

  7. Comparison of Bit Error Rates (BER) -1 10 -2 BER 10 O(K2N) MF ActMF ML ActML O(K2NL) -3 10 4 5 6 7 8 9 10 11 12 Signal to Noise Ratio (SNR) Simulations - AWGN Channel Detection Window = 12 SINR = 0 Paths =3 Preamble L =150 Spreading N = 31 Users K = 15 10000 bits/user MF – Matched Filter ML- Maximum Likelihood ACT – using inversion CAIN Project

  8. DSP Implementation • Advantages • Programmability • Ease of implementation • High Performance • Low Cost • Disadvantages • Improvements necessary to meet real-time requirements! • Sequential Processing • Parallelism not fully exploited • Cannot process or store data at granularity of bits. CAIN Project

  9. VLSI Implementation • Task Partition Algorithm into Parallel Tasks • Take Advantage of Bit Level Operations • Find Area-Time Efficient Architecture • Meets Real-Time Requirements! Task A Task C Task B Time CAIN Project

  10. Conclusions • Better Performance achieved by • Modifications in the Algorithm • Application Specific Architectures • Algorithmic Modifications • reduce the complexity of the algorithms • develop sub-optimal or iterative schemes. • Custom hardware solutions • bit level operations and parallel structure. • Together, algorithm simplifications and custom VLSI implementation can be used to meet the performance requirements of the Base-Station Receiver. CAIN Project

  11. Future Work • Analysis for Detection and Decoding • Mobile Handsets • Mobile handsets have similar algorithms • Need to account for POWER too. • General Purpose Enhancements [But, VLSI first ] • Explore Instruction Set Extensions / Architectures for DSPs • Exploit Matrix Oriented Structures • Bit Level Support • Complex Arithmetic CAIN Project

  12. 0 10 MF - Static MF - Tracking ML - Static ML - Tracking -1 10 BER -2 10 -3 10 4 5 6 7 8 9 10 11 12 SNR Fading Channel with Tracking Doppler Frequency = 10 Hz, 1000 Bits,15 users, 3 Paths CAIN Project

  13. Talk Outline • Introduction • Need for better Architectures • Channel Estimation - An example • Simulation Results • Implementation Issues • General Purpose/Application Specific • Conclusions • Future Work CAIN Project

More Related