1 / 8

IO Interfaces and Bus Standards

IO Interfaces and Bus Standards. Interface circuits. Consists of the cktry required to connect an i/o device to a computer. On one side we have data bus signals for address, data and control.

nami
Download Presentation

IO Interfaces and Bus Standards

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. IO Interfaces and Bus Standards

  2. Interface circuits • Consists of the cktry required to connect an i/o device to a computer. • On one side we have data bus signals for address, data and control. • On the other side we have a data path with its associated control to transfer data between the interface and the i/o device. This side is called port. • Parallel port • Serial port

  3. Functions of I/O interface ckt • Provides a storage buffer for at least one word of data • Contains status flags that can be accessed by the processor to determine whether the buffer is full or empty • Contains address decoding cktry to determine when it is being addressed by the processor. • Generates the appropriate timing signals required by the bus control scheme. • Performs any format conversion that may be necessary to transfer data between the bus and the i/o device.

  4. Parallel port • Multiple data path is used. • Short distance • Higher speed • Usually a parallel port transfers a byte at one time.

  5. Input Interface ckt • Any input interface must use three state logic device. • Slave ready is set when either read status or read data is present. • Any read operation is performed at master ready signal active. • LSB address bit is used to identify the status read or data read.

  6. Output interface ckt • Output is latched • A0 is used to select either status or data. • Handshake signals are generated: idle, valid

  7. Combined Input/Output ckt • A0, A1 2 bits are used to select status or data registers

More Related