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DMEM

Control. reset_i. dequeue. <3 signals>. is_computation_imm. <4 signals>. is_dmem. instruction_data_i [16:0]. wen. is_sw. restart_o. is_jr_or_ldrsw. reset_i. i s_jal. ldinst_valid. instruction_valid_i. is_alu.  dmem_o. DMEM. REGFILE. rd0_o [33:0 ]. ALU. instr_i [135:0 ].

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DMEM

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  1. Control reset_i dequeue <3 signals> is_computation_imm <4 signals> is_dmem instruction_data_i [16:0] wen is_sw restart_o is_jr_or_ldrsw reset_i is_jal ldinst_valid instruction_valid_i is_alu dmem_o DMEM REGFILE rd0_o [33:0] ALU instr_i[135:0] wa[3:0] instruction_imm_i [33:0] wd[33:0] PC + 4 1 0 0 1 1 0 1 ra0[3:0] rd1_o [33:0] instruction_label_i [16:0] 0 1 0 0 0 1 1 ra1[3:0] 0 restart_addr_o[9:0] instruction_addr_i [9:0]  alu_result PC COMPUTE reg  label  instr_addr  Backend Datapath

  2. Control uses_label is_swtch has_lab_or_imm is_swtch_or_jr regfile_output [33:0] (PC + 1) + (reg << 4) label [16:0] pc_o[9:0] instruction_addr_i [9:0] +1 0 0 1 1 1 +4 1 0 1 0 0 PC Compute Module

  3. Control write_en_i read_write_req_i reset_i dmem_34_8192 din_i [33:0] dmem_34_8192 dout_o [135:0] dmem_34_8192 addr_i [12:0] dmem_34_8192 DMEM Module

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