Transistor Odds and Ends

1. Transistor Odds and Ends

2. RTL NOR

3. NOT from NOR

4. OR from NOR

5. AND from NOR

6. Combinatorial Logic • From the NOR, we have made ANDs, ORs and NOTs. And from these we can build an expression for any truth table. • Any logic that can be written in truth table form (with only reference to the current inputs) is said to be combinatorial. • Recall we can build any combinatorial circuit using ANDs, ORs and NOTs.

7. Example: Majority Rules If two or more of the three inputs are high, then the output is high.

8. Row Expressions The highlighted rows correspond to the high outputs.

9. Sum of products • Each row is represented by the ANDing of inputs and/or inverses of inputs. • E.g. A’BC • Recall that ANDing is like Boolean multiplication • The overall expression for the truth table is then obtained by ORing the expressions for the individual rows. • Recall that ORing is like Boolean addition • E.g. A’BC + AB’C + ABC’ + ABC • This type of expression is known as a sum of productsexpression.

10. Majority rules • A´BC + AB´C + ABC´ + ABC NOTs OR ANDs

11. Other Logic Families • As one has an increasing number of logic gates one has to be concerned with their power performance and stability. • The logic gates can be made out of various combinations of resistors, diodes, and transistors. They differ in power and stability. • Let us examine an inverter from the TTL (transistor-transistor logic) family.

12. TTL Inverter

13. TTL Inverter

14. On-Off • Recall that a transistor can be thought of a switch. • When the switch is off, the transistor has very high resistance. • When the switch is on, the transistor has relatively low resistance. • It “transfers resistances.”

15. Transistor etymology

16. Totem Pole • The right-hand side of the TTL inverter is an arrangement of transistors known as a totem pole. • The transistors are arranged to that one is on and one is off. • The inverter output is just above the lower transistor in the totem pole. • If the lower transistor is on, there is little voltage drop across the lower transistor and so the output voltage is close to 0 (ground).

17. Totem Pole (Cont.) • If the lower transistor is off, then there is a large voltage drop across the lower transistor and so the output voltage is high. • One is almost directly connected to the high or the ground giving this arrangement good power/stability characteristics.

18. Similar arrangement/Opposite idea • In the totem pole arrangement, one guarantees that one of the two transistors in on and the other is off – giving a low-resistance connection to high or low as the case may be. • If we arrange for a third possibility that both transistors are off, then there is a high resistance between the output and both the high and the low. • This high-resistance or high-impedance state is neither high nor low, but effectively disconnected.

19. Poor Man’s TriState

20. Poor Man’s TriState

21. Poor Man’s TriState

22. Poor Man’s TriState

23. Same idea as the tri-state buffer • This circuit has the essential ingredients to make a tri-state buffer. • Recall that tri-state buffers are used in conjunction with buses. • When one has several devices that could place their information on the bus (“drive the bus”) only one of them should. • If two devices attempt to drive the bus to opposite voltage levels, there will be a short.

24. Three State Logic

25. Tri-state buffer Compare the Electronics Workbench tri-state buffer to the previous circuit made of transistors and logic gates.

26. In the high impedance state

27. In the high impedance state

28. In the “enabled” state

29. In the “enabled” state

30. Sequential Logic • Whereas combinatorial logic depends only on the current inputs, sequential logic can also depend on the previous “state” of the system. • Circuitry designed to hold a high or low state is known as a flip-flop. • A flip-flop is the smallest unit of RAM – random access memory. • Recall there are two basic categories of RAM: dynamic RAM (DRAM) and static RAM (SRAM).

31. Flip Flops • Flip-flops serve as the elementary units for memory in digital systems. Two features are needed: • 1. The circuit must be able to “hold” either state (a high or low output) and not simply reflect the input at any given time. • 2. But in some circumstances, we must be able to change (to “set” and “reset”) the values.

32. Remembrance of states past • The way in which the previous state information is held is different for different types of memory • In DRAM (dynamic random access memory), the state (1 or 0) is held by a charge (or lack thereof) remaining on a capacitor • Charges tend to leak off of capacitors, which is why DRAM must be periodically refreshed

33. Simple DRAM (Reset)

34. Simple DRAM (Set)

35. Simple DRAM (Hold)

36. Simple DRAM (Hold)

37. Simple DRAM (Reset)

38. Simple DRAM (Hold)

39. Simple DRAM (Hold)

40. SRAM • In SRAM (static random access memory) the history dependence is achieved via a feedback mechanism. • Feedback: the return of part of the output to the input of a mechanism, process or system (source: Random House Dictionary). • SRAM does not need refreshing, making it faster, but it is more expensive; typically it is reserved for caching and other high-speed situations.

41. RS Flip Flop feedback

42. Electronics Workbench info on RS flip-flop

43. RS Flip Flop • The Q output is inverted and fed back in as an input • Similarly the Q’ output is inverted and fed back in as an input • As suggested by the names Q and Q’, these outputs are supposed to be inverses of one another

44. The hold operation • The S=0, R=0 is the hold “state”, the flip flop keeps its previous outputs • Imagine Q=1 and Q’=0, • Then Not Q’ (which is 1) is ORed with S giving a 1 for the Q output • Then Not Q (which is 0) is ORed with R giving a 0 for the Q’ output • The output is the same as the input (no change)

45. The hold operation • The S=0, R=0 is the hold “state”, the flip flop keeps its previous outputs • Imagine Q=0 and Q’=1, • Then Not Q’ (which is 0) is ORed with S giving a 0 for the Q output • Then Not Q (which is 1) is ORed with R giving a 1 for the Q’ output • The output is the same as the input (no change)

46. The set operation • The S=1, R=0 is the set “state”, the flip flop force Q=1 • Imagine Q=0 and Q’=1, • Then Not Q’ (which is 0) is ORed with S giving a 1 for the Q output • Then Not Q (which is now 0) is ORed with R giving a 0 for the Q’ output • The Q output is forced to be (set to) 1

47. The set operation • The S=1,R=0 is the set “state”, the flip flop forces Q=1 • Imagine Q=1 and Q’=0, • Then Not Q’ (which is 1) is ORed with S giving a 1 for the Q output • Then Not Q (which is 0) is ORed with R giving a 0 for the Q’ output • The Q output is forced to be (set to) 1

48. The reset operation • The S=0,R=1 is the reset “state”, the flip flop forces Q=0 • Imagine Q=0 and Q’=1, • Then Not Q’ (which is 0) is ORed with S giving a 0 for the Q output • Then Not Q (which is 1) is ORed with R giving a 1 for the Q’ output • The Q output is forced to be (reset to) 0

49. The reset operation • The S=0,R=1 is the reset “state”, the flip flop forces Q=0 • Imagine Q=1 and Q’=0, • Then Not Q’ (which is 1) is ORed with S giving a 1 for the Q output • Then Not Q (which is now 0) is ORed with R giving a 1 for the Q’ output • Then Not Q’ (which is now 0) is ORed with S giving a 0 for the Q output • The Q output is forced to be (reset to) 0

50. The undesired operation • The S=1,R=1 is the undesired “state” • Imagine Q=0 and Q’=1, • Then Not Q’ (which is 0) is ORed with S giving a 1 for the Q output • Then Not Q (which is now 0) is ORed with R giving a 1 for the Q’ output • And so on • The Q and Q’ outputs are equal, which is undesired