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A 1V 10-Bit 400MS/s Current-Steering D/A Converter in 90-nm CMOS Chueh-Hao Yu, Wen-Hui Chen, Day-Uei Li, and Wan-Ju Huang, 2007 International Symposium on VLSI Design, Automation and Test. VLSI-DAT 2007, pp. 1 - 4, 25-27 April 2007. National Changhua University of Education
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A 1V 10-Bit 400MS/s Current-Steering D/A Converterin 90-nm CMOSChueh-Hao Yu, Wen-Hui Chen, Day-Uei Li, and Wan-Ju Huang,2007 International Symposium on VLSI Design, Automation and Test. VLSI-DAT 2007, pp. 1 - 4, 25-27 April 2007. National Changhua University of Education Department of Graduate Institute of Integrated Circuit Design Adviser : Xu-Zhong Yi Advisee : Zheng-Yuan Yang
Outline • ABSTRACT • INTRODUCTION • ARCHITECTURE • SIMULATION RESULTS • CONCLUSION
ABSTRACT • A 90 nm CMOS 1V 10-bit 400MS/s digital-to-analog converter. • Current-steering architecture segmented into 6 MSB unary and 4 LSB binary-weighted cells. • 1 V supply for the DAC core and 2.5 V for I/O interface. • Its active area is 0.51 x 0.55 mm2.
INTRODUCTION • Current-steering DACs are considered as an appropriate architecture for high-speed applications. • DACs with excellent frequency-domain performances and update rate beyond 200MS/s are necessary for the requirements of recent wireless communications.
ARCHITECTURE 6MSBs 4LSBs
Require minimum unit source area vs. overdrive voltage The p-type high-threshold voltage transistor of more than 35um2 at an overdrive voltage of 0.15V are chosen to alleviate the random mismatch error. >35
Required output impedance of the current cell 1.3M The design was made for both the INL and DNL less than ½ LSB with a SFDR lager than 70dBc. The required output impedance must be lager than 1.3M Ohm to achieve a 10-bit resolution.
SIMULATION RESULTS(1) • Output spectrum SFDR=54dB SFDR=64.4dB
SIMULATION RESULTS(2) • Dynamic performance: