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Interrupts & Cache Memory Week 3

Interrupts & Cache Memory Week 3. Computer Architecture. Review Computer Structures. English words & ideas you must know: OPCODE (Operation Code) Address Instruction Fetch Instruction Execute Instruction Set Operator Operand PC (Program Counter) IR (Instruction Register)

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Interrupts & Cache Memory Week 3

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  1. Interrupts & Cache MemoryWeek 3 Computer Architecture Computer Architecture

  2. Review Computer Structures • English words & ideas you must know: • OPCODE (Operation Code) • Address • Instruction Fetch • Instruction Execute • Instruction Set • Operator • Operand • PC (Program Counter) • IR (Instruction Register) • PSR (Program Status Register) [or PSW – Program Status Word] • MAR (Memory Address Register) • MBR (Memory Buffer Register) [or MDR – Memory Data Register] Computer Architecture

  3. What we will learn today • Review last class • Interrupts • Bus Interconnection • Cache Memory • Homework Computer Architecture

  4. Functional View of Computer • Data Processing • Data Storage • Data Movement • Control Computer Architecture

  5. Structural View of a Computer • Central Processing Unit (CPU) • Control Unit • Arithmetic Logic Unit (ALU) • Registers • CPU Interconnections • Main Memory • Input / Output (I/O) • System Interconnections Computer Architecture

  6. I/O Devices • Mouse • Keyboard • Printer • Scanner • Floppy Disk • Hard Drive • CR-ROM • DVD • Speakers • Microphone • Etc…. Computer Architecture

  7. Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction The Machine Cycle - Review Obtain an instruction from the memory Determine required actions and instruction size Locate and obtain operand data Compute a result value or status Deposit results in storage for later use Determine the successor instruction Computer Architecture

  8. Opcode Examples - Review Instruction Format Examples of Opcodes: 0001 = Load AC from Memory 0010 = Store AC to Memory 0101 = Add to AC from Memory OPCODE Address Computer Architecture

  9. CPU components - Review Control Unit: generates control signals that causes the execution of an instruction or the fetch of another instruction Program Counter: contains the address of the instruction currently being executed or the one to be fetched next Processor Status Register: contains information about the state of the CPU Instruction Register:contains the instruction currently being executed Memory Address Register: holds main memory addresses when fetching instructions or data Memory Data Register: stores instruction and data just fetched and data to be written to the main memory Arithmetic-Logic Unit:where calculations and manipulations take place General Purpose Registers:special memory cells for temporary storage of data Computer Architecture

  10. Basic Computer - Review CPU Main Memory BUS PC MAR IR MBR I/O AR Execution Unit (ALU) I/O BR I/O Units Disk, Keyboard, Monitor, etc Computer Architecture

  11. Interrupts • A mechanism by which other modules (like I/O, memory, etc) may interrupt the processor (CPU) • WHY!?? • All processing is done by the CPU • It must handle ALL requests / work Computer Architecture

  12. Types of Interrupts • Program • Usually error condition – divide by zero, overflow, memory address error, illegal instruction, etc • Timer • Timer with in CPU • I/O • I/O Controller, I/O completed or error • Hardware Failure • Power failure • Memory parity error Computer Architecture

  13. How Interrupts work • CPU MUST do all work, so: • Save current state (to where?) • Load new state (from where?) • Execute code • Restore old state (from where?) • Continue with original program Computer Architecture

  14. Interrupts – Save State • Save / restore current state to / from RAM • Save PC (Program Counter) • Save Registers • Save PSR (Program Status Register) Computer Architecture

  15. Basic BUS Structure CPU RAM I/O Computer Architecture

  16. Computer BUS • High speed data interconnect • Parallel (many data & control wires) • Connects many components in the computer • CPU • Memory • I/O • Disks (hard drives & floppies) • Keyboard, Monitor, Mouse • CDrom, DVD, etc Computer Architecture

  17. BUS – Data Transfers • Memory to Processor (CPU) • Processor (CPU) to Memory • I/O to Processor (CPU) • Processor (CPU) to I/O • Special case (special hardware) • I/O to Memory • Memory to I/O Computer Architecture

  18. Memory Constraints • Fast memory – cost MORE per bit • More memory – cost less per bit • More memory – slower access time • In summary: • Fast memory is small & expensive (Cache) • Large memory is slow & cheap (RAM) Computer Architecture

  19. Memory Characteristics • Location – Processor, Internal, External • Capacity – Word size, Number of words • Unit of Transfer – Word, Block • Performance – Access time, Cycle time, Transfer rate • Access Method – Sequential, Direct, Random, Associative • Physical Characteristics – Volatile/Nonvolatile, Erasable/Nonerasable • Physical Type – Semiconductor, Magnetic, Optical, Magneto-optical Computer Architecture

  20. Memory Hierarchy • Motherboard • CPU – registers, cache • Main memory (RAM) • Computer • Hard drives, floppies • CD-ROM, DVD • External • Magnetic tape • USB (Universal Serial Bus) devices • WORM (Write Once, Read Many) Computer Architecture

  21. Cache Memory • What is the purpose of cache memory? • Typical RAM Speed 800 MHz • Typical CPU Speed 3.2 GHz (= 3200 MHz) • CPU is 4 times faster than RAM!!! • Adapt to speed (clock speed) difference between main memory (RAM) and CPU. Computer Architecture

  22. Updated Basic Computer CPU Main Memory BUS PC Cache Memory MAR IR MBR Execution Unit (ALU) I/O AR I/O BR Registers Control Unit I/O Units Disk, Keyboard, Monitor, etc Computer Architecture

  23. Cache • How it works: • Move a block of memory (data or instructions) from RAM to Cache memory on CPU • Execute ‘most’ instructions from Cache • Accessing data ‘mostly’ in Cache Computer Architecture

  24. PROGRAM A int array[1024][1024]; int i,j; for (i=0; i<1024; i++) { for (j=0; j<1024; j++) { array[i][j] = 0; } } PROGRAM B int array[1024][1024]; int i,j; for (j=0; j<1024; j++) { for (i=0; i<1024; i++) { array[i][j] = 0; } } Cache ExampleC - Code Computer Architecture

  25. Cache Memory – Optional Material • Main Cache Design Characteristics • Cache Size • Mapping Function • Direct • Associative • Set Associative • Replacement Algorithm • LRU – Least Recently Used • FIFO – First In First Out • LFU – Least Frequently Used • Random • Write Policy • Write through • Write back • Write once • Number of caches • 1 Or 2 levels • Unified or split Computer Architecture

  26. What you know now • Interrupts • Bus Connections • Cache Memory Computer Architecture

  27. Reading • Interrupts http://en.wikipedia.org/wiki/Interrupt • Cache http://en.wikipedia.org/wiki/CPU_cache • RAM http://en.wikipedia.org/wiki/Random-access_memory Next Lecture • Internal Memory Computer Architecture

  28. Self-Preparation QuestionsWeek 3 1. Draw a detailed diagram of a CPU.2. Why do we need interrupts?3. What is the purpose of cache memory? Computer Architecture

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