Seoul Korea December 9, 2008

1. International Technology Roadmap for Semiconductors Assembly and Packaging 2008 Seoul Korea December 9, 2008

2. Assembly and Packaging Technical Working Group Participants for 2008 60 Active participants with representation from Europe, Japan, Korea, Taiwan and the United States

3. Major Activities • Completed System in Package Paper The next Step in Assembly and Packaging: System Level Integration in the package (SiP) Published on the ITRS web site • Held 8 face to face meetings in 6 countries • Began work on major revisions required in 2009

4. Rapid Changes in Package Technology A gap exists between the time CMOS scaling can no longer maintain progress at Moore’s Law rate and when a new switch is ready. Packaging innovation is enabling: • equivalent scaling through functional diversification • density increase through 3D packaging A new generation of package architectures are needed to support increase in functional density and decrease in cost per function.

5. New Package Types are Gaining Market share

6. New Packaging Requirements Stimulate Development of new Technolofies with Difficult Challenges Typical SiP 2010

7. New Packaging Requirements Stimulate Development of new Technologies with Difficult Challenges remaining Stacked die Wafer level packaging Through silicon vias Embedded components (active and passive) Wafer thinning Wafer to wafer bonding Die to wafer bonding New materials and more

8. These Technologies are in Prototype Today WL-Assembly die (TSV) to wafer IC1 Tungsten filled TSV: Depth 50 µm IC2 PCB IC1 IC1 with TSV and Front / Backside RDL CuSnCu Interconnects IC2 with Front Side RDL IC2 PCB Source: Fraunhofer IZM

9. Applications for New Materials • In this decade most, if not all packaging materials will change due to changing functional and regulatory requirements • Bonding wire • Molding compounds • Underfill • Thermal interface materials • Die attach materials • Substrates • Solder • In the next decade most will change again with the introduction of nanoparticles, new molecules and nanotubes

10. Cu interconnect Ultra Low k dielectrics High k dielectrics Organic semiconductors Green Materials Pb free Halogen free New Materials Many are in development Many are in use today • Nanotubes • Nano Wires • Macromolecules • Nano Particles • Composite materials

11. Difficult Challenges >22nm • 9 Categories identified • Impact of BEOL including Cu/low κ • Wafer level CSP • Co-design and simulation tools • Embedded components • Thinned die issues • Gap between Chip and Package cost trend • High current density packages • Flexibility requirements for packages • 3D packaging

12. Difficult Challenges -Reliability -Wafer/die handling -Testability -System level co-design needed now -EDA for “native” area array -Models for reliability prediction Thin Wafers EDA Tools Reliability of Low k -Reliability of first level interconnect with low κ -Interfacial adhesion -Improved fracture toughness of dielectrics

13. Difficult Challenges -Thermal management -Through wafer via structure and via fill process - Test access for individual wafer/die Performance at low Cost -Increased wireability at low cost -Improved planarity and low warpage at higher process temperatures -Increased via density in substrate core 3D Packaging

14. Difficult Challenges <22nm • 5 Categories identified • Package cost reduction curve • Small die with high power and pin count • High frequency • System level design capability • Emerging device types • Organic devices • Nanostructures and materials • Biological interfaces

15. Difficult Challenges • -Lower loss dielectrics • Skin effect above 10 GHz • There is currently a “brick wall” at five micron lines and spaces • “Hot spot” thermal management High frequency Die Emerging device types (organic, nanostructures, biological) that require new packaging technologies

16. The Rapid Pace of Change Required Major Revisions • Warpage at peak temperature (AP4b) New table added to address warpage • Package Level System Integration (AP9) Changed to provide quantitative projections • Technologies and processes for SiP (AP10)Increased detail, segmented by process • Automotive Operating Environment Specifications (AP21)New table added to address automotive packaging requirements

17. Warpage is a Major Factor with shrinking pitch, thinner packages There are standards for room temperature warpage in process through JEDEC. They do not address the problems at maximum temperature A section will be added to the 2009 Roadmap to address this in detail

18. Package Level System Integration Most of the colored cells are due to cost or thermal management challenges

19. Automotive Packaging The rapid growth in hybrid and electric vehicles brings an additional class of electronics and a new subset of environmental conditions that will be addressed in the 2009 Roadmap. This is not reflected in the 2008 table.

20. Major Changes Planned for 2009 • Expanded coverage of 3D TSV technology • Time table of the introduction of a new generation of materials • Revised warpage treatment to address problems at high temperatures • Expansion of automotive electronics • New coverage of packaging problems due to the transition to 450mm wafers • Expanded coverage of new MEMS device types including a new table • Expanded coverage of optical communication, photo voltaic devices and lighting • Increased coordination with other TWGs

21. THANK YOU