Microcomputer Principle and Interface Technology - Introduction

1. Microcomputer Principle and Interface Technology - Introduction 计算机学院 李征 Tel：13882153765 Email：lizheng@cs.scu.edu.cn OICQ: 1340915

2. Course Content • Architecture and Mechanism of 8088/8086 CPU • 8088/8086 Instruction System and Programming with Assembler Language • Architecture and Mechanism of PC System (PC Bus) • Basic I/O Interface and Basic Programming for I/O Interface

3. Content of this chapter • 1. Basic architecture of microcomputer • 2. Basic signals and temporal procedure in microcomputer • 3. Machine instruction and assembler language

4. Essential Parts of Computer • Center Process Unit • Bus • Memory • I/O Interface • I/O Device • Five essential parts are necessary for all computers.

5. General Architecture of Computer CPU Memory Bus（Data, Address, Control） I/O Interface I/O Interface I/O Interface I/O Device I/O Device I/O Device

6. Essential Storage Cell in Computer • Register in CPU • Memory Cell • I/O Port (Register in I/O Interface) • Three types of essential storage cell in all computers. • Questions: • 1. What is the main function of the bus? • 2. What do our programs mainly do?

7. Address • Every storage cell has an unique address. • The address must be provided on the bus before a storage cell can be operated.

8. Binary Information • Although we use decimal numbers in the program design, all information in computer is binary. • There only two signal types in computer, which is 0 and 1. • The basic unit of a storage cell is bit.

9. Basic storage unit 维持 置1 清0 非法 SD RD Qn Qn+1 Q Q 1 1 0 1 1 0 1 1 0 0 1 1 0 0 1 1 1 1 0 0 0 0 0 1 0 1 0 1 0 1 0 1 1 1 0 0 1* 1* 1 1 0 1 1 0 SD RD 0 1

10. Basic storage unit

11. Basic Address Unit - Byte • Byte is composed of 8 bits. • In microcomputer, every unique storage cell in memory is a byte which has an unique address. • Word length is the maximal bit number which CPU can process synchronously.

12. (1) Center Process Unit Pentium 4 80386 Pentium 8088CPU

13. (1) Center Process Unit • (1) CPU control other parts of computer with temporal logic automatically. • (2) CPU execute programs in the memory.

14. Temporal Procedure • Temporal procedure is the control procedure performed step by step and orderly. • Two types of temporal procedure are performed by CPU.

15. Temporal Procedure • 1) Non-instruction execution: • reading instruction bytes from memory, • Interrupt procedure, etc. • 2) Instruction execution (Program is composed of instructions stored in memory)

16. Most operations in temporal procedure • reading or writing registers in CPU, memory cell, or I/O port • performing arithmetic or logic operation with ALU (Arithmetic Logic Unit)

17. (2) System Bus PCIBus ISABus

18. (2) System Bus • Bus provide necessary signal connections between CPU, memory and I/O Interface. • There are three types of bus in bus architecture, which are address bus, data bus and control bus.

19. (2) System Bus System Bus Address Bus ( AB) Bus Generator Data Bus (DB) Control Bus (CB) CPU Subsystem Memory I/O Interface I/O Device Microcomputer Architecture

20. Bus Operation in Temporal Procedure • When memory cell or I/O port is to be operated, bus operation is necessary in temporal procedure. • Operation of registers in CPU does not need system bus.

21. Address Bus • Cell Address must be provided on address bus when cell is to be operated (reading or writing). • Generally, higher part of address is for chip selection, and lower part of address is for cell selection. • Address bus is unidirectional bus.

22. Data Bus • When CPU write a binary data to a memory cell or I/O port, it output data signals to data bus. • When CPU read a binary data from a memory cell or I/O port, it input data signals from data bus. • Data bus is bidirectional.

23. Control Bus • CPU send basic control signals by control bus to memory or I/O interface. (For example, RD and WR signals). • I/O interface send basic status signals by control bus to CPU (For example, Interrupt signal). • Observed individually, Control bus is unidirectional. As a whole, it is bidirectional.

24. (3) Memory

25. (3) Memory • Memory is the storage center of computer. • If a program is expected to be performed, it must be loaded in memory first. • The instructions which form the program, and the data which used by program are all stored in memory.

26. (4) I/O Interface • I/O interface is a circuit which connect the system bus and I/O device. • Why there is an interface needed between bus and device? • 1) Signal Difference: Signals in I/O devices is much different from signals in system bus. • 2) Transfer Rate Difference: Data transfer rates of I/O device and CPU may be very different.

27. (4) I/O Interface

28. I/O Port • Registers in I/O interface are called I/O ports in program design. • There are three types of I/O port in interface, which are data, command, status port separately.

29. Functions of I/O Interface • 1) It provides signal transformation between I/O device and system bus. • 2) It provides data buffer to avoid data lost in transfer because of the transfer rate difference between device and CPU.

30. Functions of I/O Interface • 3) It provides interaction ways between CPU and I/O devices. • 4) It make devices can be controlled by program.

31. Signal Transformation • 1) Transformation between Analog signal and Digital signal • Example: Sound input and output • 2) Transformation between different digital signals

32. Signal Transformation • For input device, input signal is transformed to binary data, and stored in data port by interface, waiting for reading by CPU. • For output device, CPU writes the output binary data into data port, waiting for outputting by interface.

33. Data Buffer • For input device, if device provides an input when CPU is busy, the interface stored the input data in data port. • For output device, if CPU provides an output when interface is busy, the interface stored the output data in data port.

34. Interaction between I/O interface and CPU • 1) CPU send commands to interface with command port. • For example: • Setting the operation mode of interface or device

35. Interaction between I/O interface and CPU • 2) CPU check the status of the interface with status port. • For example: • CPU check the input status to know if there is input data in data port. • CPU check the output status to know if the output data in data port has been outputted.

36. Interaction between I/O interface and CPU • 3) Interrupt (active status) • For example: • If there is input data in data port, interface send interrupt signal to CPU.

37. Programmable Interface • CPU interacts with I/O interface by I/O port operations (mostly by I/O instructions). • Generally, these I/O port operations are performed orderly and logically. • If we make a program to perform these I/O port operations, this program is called a driver.

38. (5) I/O Device

39. Content of this chapter • 1. Basic architecture of microcomputer • 2. Basic signals and temporal procedure in microcomputer • 3. Machine instruction and assembler language

40. Basic Signals • Clock (CLK, sent by Clock Generator) • Read (RD, sent by CPU) • Write (WR, sent by CPU) • Chip Select (CS, generated on Address Bus) • Interrupt (INT, sent by interface) • Interrupt Acknowledge (INTA sent by CPU)

41. Clock • Clock: A periodic signal sent by clock generator, its cycle is called clock cycle（时钟周期，节拍）. • The clock signal is necessary for CPU temporal procedure. • The clock cycle is the basic time unit in temporal procedure.

42. time T Clock

43. Clock • Any temporal procedure is composed of multiple clock cycles. • The clock cycle also used to describe the process speed of CUP. • Shorter cycle implied faster processing.

44. Read and Write • The bus operations (temporal procedure with system bus) performed by CPU can be summarized as reading and writing. • When CPU expect to read or write a memory cell or I/O port, it sends read or write signal to control bus.

45. Reading and Writing Cycle • The time consumed in reading or writing procedure is always composed of multiple clock cycles. • The time consumed in reading or writing procedure is called reading or writing cycles.

46. Chip Select • When CPU expect to read or write a cell outside, cell address must be provided on the address bus. • The address decoder (on address bus or in chips) decode the higher part of cell address to generate chip select signal. • Chip select signal is used to select memory chip or I/O interface chip, and the lower part address is used to locate the cell.

47. Address Decoder Address Decoder Output：<=2n Input：n

48. Chip Select • Important: Only when chip select is valid for a chip, the cells in it can be operated.

49. Interrupt and Interrupt Acknowledge • When an input device expect transfer input data to CPU • or an output device expect output data from CPU, • it can send interrupt signal to CPU with control bus.

50. Interrupt and Interrupt Acknowledge • If interrupt acknowledge of CPU is allowed, • and when the current instruction has been finished by CPU, • CPU send interrupt acknowledge signal to I/O interface.