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Wires & wire delay

Wires & wire delay. Lecture 9 Tuesday September 27, 2016. Outline. Introduction Interconnect Modeling Wire Resistance Wire Capacitance Introducing a distributed wire RC p -model Estimating wire RC d elay assuming a dominant time constant Elmore delay model – a generalized model

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Wires & wire delay

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  1. Wires & wire delay Lecture 9 Tuesday September 27, 2016

  2. Outline • Introduction • Interconnect Modeling • Wire Resistance • Wire Capacitance • Introducing a distributed wire RC p-model • Estimating wire RC delay assuming a dominant time constant • Elmore delay model – a generalized model • Handling wire branches • Inserting repeaters to keep wire lengths short Introduction to Integrated Circuit Design

  3. Introduction • Chips are mostly made of wires called interconnect • In stick diagram, wires set size • Transistors are little things under the wires • Many layers of wires • Wires are as important as transistors • Speed • Power • Noise • Alternating layers run orthogonally • Odd metal wires • Even metal wires Introduction to Integrated Circuit Design

  4. Modern interconnect Metal 6 Via 5-6 Metal 5 Metal 4 Metal 3 Metal 2 Via 1-2 Metal 1 Local Tungsten interconnect Introduction to Integrated Circuit Design

  5. Choice ofmetals • Until 180 nm generation, most wires were aluminum • Contemporary processes normally use copper • Cu atoms diffuse into silicon and damage FETs • Must be surrounded by a diffusion barrier Introduction to Integrated Circuit Design

  6. Layer stack • AMS 0.35 mm process has 3 metal layers • M1 for within-cell routing • M2/M3 for vertical/horizontal routing between cells • Modern processes use 6-10+ metal layers • M1: thin, narrow (< 1.5*minimum feature size) • High density wiring in cells • Mid layers: thick, wide • Global interconnect • Top layers: THICK, WIDE • For VDD, GND, clk Introduction to Integrated Circuit Design

  7. Sheet resistance Just count number of squares along wire and multiply with RS When W=L the resistance is equal to R0, the sheet resistance (i.e. the resistance of a square wire) t t R0=r/t Other books use RS W W All wires in a layer have the same thickness t L L Introduction to Integrated Circuit Design

  8. Wire geometry Pitch = w + s • w • w>>t t Old technology Modern technology • Today: pack in many skinny wires! • For long skinny wires resistance cannot be neglected since cross sectional area shrinks with feature size, wire length stays the same or increases. Hence: we need a wire RC model Introduction to Integrated Circuit Design

  9. Example • Compute the sheet resistance of a 0.22 mm thick Cu wire in a 65 nm process. The resistivity of thin film Cu is 22nW.m. • Find the total resistance if the wire is 0.125 mm wide and 1 mm long. (Ignore the barrier layer) Introduction to Integrated Circuit Design

  10. Wire delay scaling – Local wires stays constant • For local wire crossing the same amount of circuitry • Resistance stays roughly constant • Length decreases by same amount as width, height stays large and/or change material to copper • Capacitance decreases by scaling factor • Cap/unit length stays constant, length decreases • Wire delay tracks improvement in gate delay Wire length L, width W Wire length L/S, width W/S stays constant From Mark Horowitz at Design Automation Conference 2000 Introduction to Integrated Circuit Design

  11. From Mark Horowitz at Design Automation Conference 2000 Wire delay scaling – Global wires stays constant • For global wire crossing the whole chip • Resistance grows linearly (with scaling factor) • Capacitance stays fixed • Wire delay increases relative to gate delay Wire length L, width W Wire length L, width W/S stays constant Introduction to Integrated Circuit Design

  12. S = S Local Technology S = S Global Die Modern Interconnect Global Interconnect Source: Intel Introduction to Integrated Circuit Design

  13. Wire capacitance Bottom plate and fringe capacitance Wire has capacitance c per unit length • to neighbors • to layers above and below Parallel plate capacitance equation • C = eoxA/d • eox=ke0, k≈4 for SiO2, low-kappa k<3 Note: Cap is per unit length Introduction to Integrated Circuit Design

  14. Metal2 Capacitance Data • Typical wires have ~ 0.2 fF/mm, i. e. 200 fF/mm • Compare with 1.2 fF/mm for MOSFET gate cap Data shown for s = 320, 480, 640 nm, and s = ∞ Metal 3 Metal 1 Introduction to Integrated Circuit Design

  15. Wire RC delay In any given technology • wire RC increases as L2 with wire length L • ris wire resistance per unit length • cis wire resistance per unit length Introduction to Integrated Circuit Design

  16. Step-response of RC wire as a function of time and space Introduction to Integrated Circuit Design

  17. Wire delay example • Estimate the delay of a 9X inverter driving a 4x inverter at the end of the 1 mm wire! WN=0.78 mm. WP=2WN. Assume wire cap c=200 fF/mm, r=800 W/mm from previous example Without wire, delay becomes 5 ps*(pinv+X4/X9)=5*(0.8+4/9)= 6.2 ps 9X driver inverter 4X receiver inverter 2.2 kW 1 mm long, 125 nm wide Cu wire 1.4 fF 4X 9X CG • Reff 2.6 fF CD Introduction to Integrated Circuit Design

  18. Wire delay example • Estimate the delay of a 9X inverter driving a 4x inverter at the end of the 1 mm wire! WN=0.78 mm. WP=2WN. Without wire, delay becomes 5 ps*(pinv+X4/X9)=5*(0.8+4/9)= 6.2 ps With wire cap, electrical effort increases with 200 fF/(9*0.36 fF) = 62 Delay becomes ~316 ps! 9X driver inverter 4X receiver inverter 2.2 kW 0.8 kW 1.4 fF 4X 9X CG • Reff • Rwire 2.6 fF CD 100 fF • 100 fF What if wire resistance is added? Delay increases further with 0.7*(0.8*101.4) = 56 ps to 372 ps Introduction to Integrated Circuit Design

  19. Wire delay example • Estimate the delay of a 9X inverter driving a 4x inverter at the end of the 1 mm wire! WN=0.78 mm. WP=2WN. driver inverter receiver inverter 1 mm long, 125 nm wide Cu wire 4X 9X • Wires are distributed systems • Approximate with lumped element models • In Spice simulations a 3-segment p-model is accurate to 3% For analytical solution: use single segment p-model Introduction to Integrated Circuit Design

  20. Elmore delay model • Estimate the delay of a 9X inverter driving a 4x inverter at the end of the 1 mm wire! WN=0.78 mm. WP=2WN. • Use Elmore delay model to calculate RC constant for each R: • Multiply each resistance with its downstream capacitance! p-wire model 9X driver inverter 4X receiver inverter CG • Reff • Rw CD • V0 Cw/2 • Cw/2 Introduction to Integrated Circuit Design

  21. Wire delay example • Estimate the delay of a 9X inverter driving a 4x inverter at the end of the 1 mm wire! WN=0.78 mm. WP=2WN. • RC product = (2.2 kW)(204 fF) + (0.8 kW)(101.4 fF) = 530 ps • Propagation delay = 0.7RC = 372 ps 2.2 kW 0.8 kW • Reff • Rwire CG CD 1.4 fF 2.6 fF 100 fF • 100 fF X9 X4 Introduction to Integrated Circuit Design

  22. Elmore delay model – from where? • Simplify the two-stage RC circuit! • Write nodal equations! • R2 • R1 • V1 • V2 • Vin • sC1 sC2 Introduction to Integrated Circuit Design

  23. Elmore delay model – from where? • Simplify the two-stage RC circuit! • Write nodal equations! • Matrix form • R2 • R1 • V1 • V2 • Vin • sC1 sC2 Introduction to Integrated Circuit Design

  24. Elmore delay model – from where? • Simplify the two-stage RC circuit! • Write nodal equations! • Matrix form • Invert matrix for V1 and V2! • R2 • R1 • V1 • V2 • Vin • sC1 sC2 Characteristicequation: D=det M=0 Introduction to Integrated Circuit Design

  25. Elmore delay model – from where? • Exact solution is sum of two exponentials with time constants t1=1/s1 and t2=1/s2 • As you already know, poles s1and s2are often well separated! • Hence, t1>>t2 and dominating! Bode plot Amplitude s2 frequency s1 Dominating frequency: Introduction to Integrated Circuit Design

  26. Elmore delay model – from where? • Approximate solution: • exponentialwithdominatingtimeconstantt1 • Each resistance is multiplied with its downstream capacitance! • R1 • R2 • V1 • V2 • C1 C2 • Vin Introduction to Integrated Circuit Design

  27. Approximative solution • with dominating time constant One example: R1=0.8R2, C1=1.2C2 t1=2.45, t2=0.31 Compare two-pole solution to dominating exponential Introduction to Integrated Circuit Design

  28. Elmore delay model formulation 2 Alternatememoryrule: • R1 • R2 • V1 • V2 • C1 C2 This is anotherformulationofElmore´sdelaymodel: Each capacitance is multiplied with its upstream resistance. Introduction to Integrated Circuit Design

  29. Ideal wire delay • Wire delay increases as L2 with wire length! • Keep wires short! • R1=0 • Rwire • V2 • Cwire/2 • Cwire/2 Most often t1>>t2and dominating! For an ideal voltage source (R1=0) and C1=C2=Cwire/2 we get wire delay Introduction to Integrated Circuit Design

  30. Summary • Wehaveintroduced a wire p-RC model • Wehaveanalyticallysolved for delayed output response • Wesimplifiedusing dominant timeconstant • Wearrived at Elmore´s wire delaymodel! Introduction to Integrated Circuit Design

  31. Using Elmore delay model • “What if I change driving capability of the X9 inverter, what driving capability will minimize the propagation.” • X9 RC product = (2.2 kW)(206 fF) + (0.8 kW)(103.2 fF) = 536 ps 0.8 kW • General RC product = Reff*(Cwire+2CG)+Rwire*(Cwire+2CG)/2 • Has minimum when Reff*Cwire=Rwire*CG, i.e. for • New RC product = 0.17×(200+84)+0.8×(100+42)=34+14+80+34≈160 ps • Reff • Rwire CG CG CD 0.17 kW 2.2 kW 0.8 kW 3.2 fF slightly changed capacitance values 100 fF • 100 fF • Reff • Rwire CD 42 fF X118 X9 3.2 fF 100 fF • 100 fF 42 fF X9 X118 ReffCG=7.2 ps, RwireCwire=160 ps → Reff=0.17kW, CG=7.2/0.17= 42 fF Introduction to Integrated Circuit Design

  32. Using Elmore delay model • What if I cut wire in two pieces? Total RC goes from 160 ps to 136 ps + CG CG 0.17 kW 0.17 kW 0.4 kW 0.4 kW • New RC product = 0.17×(100+84)+0.4×(50+42)=17+14+20+17≈78 ps • Reff • Reff • Rwire • Rwire C C 42 fF 42 fF X118 X118 50 fF 50 fF • 50 fF • 50 fF 42 fF 42 fF X118 X118 • New RC product = 0.17×(100+84)+0.4×(50+42)=17+14+20+17≈78 ps Introduction to Integrated Circuit Design

  33. Making Elmore delay model general “input" R1 V1 VIN C1 R2 V2 C2 R3 V3=VOUT C3 output Write nodal equations for all nodes Then multiply each nodal equation with its upstream resistance from the node to the voltage source Introduction to Integrated Circuit Design

  34. Making Elmore delay model general Add equations 1st order linear diff equation Elmore time constant Introduction to Integrated Circuit Design

  35. Handling branches Add equation for node 4 Theory behind rule of thumb for handling branches: “input" R1 R4 V1 V4 VIN C1 C4 R2 V2 C2 R3 V3=VOUT Modify node equation for node 2 C3 output Introduction to Integrated Circuit Design

  36. Three wire segments • R2 • R0 • R1 • R3 • C2/2 • C3/2 • C1/2 • C2/2 • C3/2 • C1/2 • Elmore´s delay formula: Each capacitance is multiplied by its upstream resistance! Introduction to Integrated Circuit Design

  37. Three wire segments with branches • Identify main path Introduction to Integrated Circuit Design

  38. Wire branches • Main path RC model; same as in previous example without branches • R2 • R1 • R3 • R0 • C3/2 • C3/2 • C2/2 • C2/2 • C1/2 • C1/2 • Elmore´s delay formula: As before, each capacitance is multiplied by its upstream resistance! • Alternative way of writing the same Elmore wire delay Introduction to Integrated Circuit Design

  39. Wire branches • Add branches to RC model! • R2 • R1 • R3 • R0 • Cb1/2 • Cb1/2 • Cb2/2 • Cb2/2 • Cb3/2 • Add delay due to branch capacitances • Cb3/2 • Total delay is equal to sum of main path delay and branch contributions Introduction to Integrated Circuit Design

  40. Driving long wires with repeaters • Since wire delay increases as L2 with wire length, it could be advantageous to divide long wires into segments driven by repeaters Repeater data: input and output capCrep, effectiveresistanceRrep Rw/m Rw/m Rw/m Cw/2m Cw/2m Cw/2m Cw/2m Cw/2m Cw/2m • The delay of m segments can be written • Determine the number of segments that minimizes delay: • There is a critical wire length when repeaters should be considered • The number of segments increase linearly as m, but the delay of each wire segment decreases as 1/m2 Introduction to Integrated Circuit Design

  41. How to size the repeater rep rep Crep Crep Elmore model for segment delay: RrepCrep is a constant! Two important terms for optimization: Rw/m Cw/2m Cw/2m Minimum when Optimum repeater strength Introduction to Integrated Circuit Design

  42. Summing up the segment delays • For m=mopt, we obtain the following wire delay Introduction to Integrated Circuit Design

  43. Conclusion • Importance of wire delay • Introduced distributed wire RC p-model • Discussed relevance of delay equations using a dominant time constant model • Using delay model to minimize wire delay • Elmore delay model – a generalized model • Mathematics behind Elmore model • Handling branches • Repeater insertion Introduction to Integrated Circuit Design

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