Midterm presentation Winter 2010 Performed by: Tomer Michaeli 052792769

1. Midterm presentation Winter 2010 Performed by: Tomer Michaeli 052792769 Liav Cohen 301242509 Supervisor: Shlomo Beer Gingold In collaboration with: characterization of synchronizers and metastability

2. Our project subject • Direct measurements of synchronization Circuits and comparison to measurement results by a built-in self on chip characterization unit.

3. Project goals • Learning the direct measurement method. • Building and improving the measurement system for synchronization to characterize performance of synchronizers.

4. Signal generator Test Chip 65nm FPGA board DLP socket (PC) Project environment The test environment is composed by the FPGA board that generates control and data signals for the 65nm Synchronizer test chip.

5. Achievements Learning the measurement system. Learning the chip characteristics and the measurement system GUI Initial results

6. Top level design f1=6.245 MHz f2=6.25MHz (FPGA clock) FF DATA TRIGGER DSO80204B Scope Input

7. Searching for metastability f1=6.245 MHz (data) 160.13 ns f1=6.25 MHz (clock) 160 ns FF out 200 μs • The difference between the two clocks is 130 ps. • The frequency of the FF output is 5 Khz (frequencies difference of inputs) . • The FF setup time is usually 50 ps so a metastability can occur at a 5 Khz rate. • If we determine the difference to be lower than 130 ps we get less chances for metastability. On the other hand, the probability to metastability will grow.

8. The GUI

9. Test chip- top level design (DATA)

10. Test chip- Digital logic block

11. The oscilloscope • The output of the flip-flop (FF) is connected through the PLD to the trigger input of the oscilloscope • The FPGA clock signal is connected through the PLD to the data channel of the scope • The digital sampling scope is capable of continuous data accumulation and the results are available for statistical analysis.

12. The oscilloscope • Each data point accumulated by the scope represents one sampled rising transition of the clock signal. • Its horizontal displacement indicates the delay from the clock input to the data output of the FF.

13. Initial results figure [1]

14. Previously known results [1] figure [2]

15. Initial results • In figure [2] we see the distribution of the samples propagation delay (how much longer it takes the output to be update relative to normal propagation delay). • White color indicates the largest number of cases with normal propagation delay.

16. Previously known results [2]

17. Project Schedule

18. References [1] Yaron Semiat and Ran Ginosar, ‘Timing Measurements of Synchronization Circuits’ , Technion, Haifa. [2] Shlomo Beer Gingold, ‘Test Chip (Sinc_test_chip)’, Technion, Haifa.