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Self-Healing Mixed-Signal Baseband Processor for Cognitive Radios

Self-Healing Mixed-Signal Baseband Processor for Cognitive Radios. Presented by oussama sekkat. Goal of the project. To implement a revolutionary new mixed-signal baseband processor targeting the task of spectrum sensing in cognitive radios. Will use both energy detection and pilot detection.

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Self-Healing Mixed-Signal Baseband Processor for Cognitive Radios

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  1. Self-Healing Mixed-Signal Baseband Processor for Cognitive Radios Presented by oussamasekkat

  2. Goal of the project • To implement a revolutionary new mixed-signal baseband processor targeting the task of spectrum sensing in cognitive radios. • Will use both energy detection and pilot detection

  3. Berkeley Emulation Engine 2 (BEE 2) • The platform: • 5 high-performance Xilinx FPGAs (Virtex II Pro 70) each containing a power PC Core • Support for up to 20GB of high speed DDR2 DRAM • FPGAs laid out in a star topology with four user FPGAs in a ring and one control FPGA connected to each user. • User FPGAs each have four independent high speed serial channels which are capable of transferring data at 10Gbps (XAUI interface) • 1 Ethernet port.

  4. BEE 2 (Topology)

  5. BORPH Operating System • BORPH:Berkeley Os for ReProgrammable Hardware • Extended Linux kernel that treats FPGA resources as native computational resources . • Provides integral operating system supports for FPGA designs, such as the ability for an FPGA design to read/write to the standard Linux file system. A user process in BORPH, can therefore either be a software program running on a processor, or a hardware design running on a FPGA. 

  6. BORPH Operating System (cont.)

  7. Cognitive radio test bed • Front end board contains: • FPGA board • XAUI connection • Baseband processor • Front-end radio

  8. Development environment • MSSGE tool flow: • Matlab v7.0.4 (R14) SP2 • Simulink v6.2 (R14) SP2 • Xilinx System Generator v7.1 • Xilinx EDK v7.1.02i • Xilinx ISE v7.1.04i • MSSGE libraries (Simulink models etc..)

  9. Bee2 setup • SSH connection to Bee2 enabled. • IP: 128.97.88.153 • Can use a modified RS-232 cable to connect to Bee2 as a root. • Hardware process example:

  10. Hardware process example: • Counter:

  11. Hardware process (cont.)

  12. Hardware process (cont.) • matlab >> bee_xps

  13. Hardware process (cont.)

  14. Hardware process (cont.) • In BEE 2: user@bee2% ./testborph_oussama_floating_2009_Mar_12_1523.bof & user@bee2% ps PID TTY TIME CMD26427 pts/6 00:00:00 bash26488 pts/6 00:00:00 testborph_oussama_floating_2009_Mar_12_1523.bof 26525 pts/6 00:00:00 ps user@bee2% cd /proc/26488/hw user@bee2% lsioregioreg_mode region user@bee2% cdioreg user@bee2% lscnt_encnt_val user@bee2% cat cnt_val 00000000 user@bee2% echo 1 >> cnt_en user@bee2% cat cnt_val 000AC015 user@bee2% cat cnt_val 000ACFF9 user@bee2% echo 0 >> cnt_en user@bee2% cat cnt_val 000ADEF3 user@bee2% cat cnt_val 000ADEF3

  15. Data acquisition example Start the user FPGA process: user@bee2% ./bee_1_fe_fpga1_2009_Jan_15_1238.bof &

  16. Data acquisition example Start the control FPGA process: user@bee2% ./bee_cntlfpga_2009_Jan_22_1215.bof &

  17. Data acquisition example

  18. Data acquisition example user@bee2% ./init // Initialize front end user@bee2% ./status 0 // Status for front end 0 --RF-- FE 0: frequency 2445 FE 0: ant_select 0 FE 0: tx_on 1 FE 0: tx_power 7 FE 0: rx_lna_gain 0 FE 0: refadj 0 FE 0: rx_agc 120 --MxFE-- FE 0: clkout1_div 0 FE 0: clkout2_div 0 FE 0: tx_dac_gain 128 FE 0: tx_pga_gain 100 FE 0: tx_two_edges 0 FE 0: tx_inv_sample 0 FE 0: tx_twos_complement 0 FE 0: tx_inv_sync 0 FE 0: tx_q_i_order 0 FE 0: tx_retime 0 FE 0: tx_interpolate 0 FE 0: tx_hilbert 0 FE 0: tx_keep_ve 0 FE 0: rx_pga_a 15 FE 0: rx_pga_b 15 FE 0: rx_dcs_ena 0 FE 0: rx_hs_duty_cycle 0 FE 0: rx_decimate 0 FE 0: rx_hilbert 0 FE 0: rx_keep_ve 0 FE 0: rx_inv_sync 0 FE 0: rx_twos_complement 0 FE 0: rx_retime 0 FE 0: mxfe_spi_raw 0x00000000 FE 0: rssi_config 0x00000000 • --TxDatapath-- • FE 0: tx_sync_ena 1 • FE 0: tx_data_sel 1 • FE 0: tx_offset_i 120 • FE 0: tx_offset_q 120 • FE 0: tx_rate_i 3 • FE 0: tx_rate_q 3 • FE 0: tx_amplitude_i 0 • FE 0: tx_amplitude_q 0 • FE 0: tx_stepsize 1000 • FE 0: tx_signal_mem_1 0x00000000 • FE 0: tx_signal_mem_2 0x000100ff • terminal count 255 • step size 1 • FE 0: tx_signal_mem_3 0x00000001 • enable mask 0x1 • FE 0: tx_ext_up_dn_ena 0 • FE 0: tx_ext_up_dn 0 • FE 0: tx_ext_data_i 0 • FE 0: tx_ext_data_q 0 • --RxDatapath-- • FE 0: rx_test_sel 0 • FE 0: rx_fft_sel 0 • FE 0: rx_set_bias 0 • FE 0: rx_resolution 0 • --ChipScope-- • local: scope 0 • --HopControl-- • local: hop_config_1 0x00000000 • local: hop_config_2 0x00000000

  19. Data acquisition example user@bee2% ./sigmem spectra/14bit/256_10.txt // load signal from given file user@bee2% ./param tx_on 1 // set parameter tx_on of front end 0 to 1

  20. Bee2 and CR test bed demo DEMO

  21. Next steps • Use the ./acquire utility to capture received signal and transfer it to BEE2 file system • Use the extract_raw script to convert the binary dump file created by the “acquire” utility into a format readable my Matlab • Run fft_rx matlab script on the resulting file.

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