Embedded Systems Design at Mentor

1. Embedded Systems Design at Mentor

2. Platform Express Drag and Drop Design in Minutes Simple System Diagrams represent complex designs. IP Described In XML Databooks Consistent HW and SW Programmers View

3. Advanced IP Configuration Options • Statically Configured IP • Configuration options are generated automatically. • Dynamically Configured IP • Generated as part of the design creation/context process. • Platform Transforms • Auto-customization of IP for specific design contexts.

4. Creating The Design HDL • Choice of Verilog and VHDL. • Targeted for Modelsim and other simulators. • Auto-Generation of HDL bus infrastructure. • Platform Express is bus agnostic. • Proprietary and custom bus formats are easily supported.

5. Creating A Complete Verification SoC Environment • Seamless HW/SW Co-verification • Modelsim HDL Simulation • XRAY Embedded Debugger

6. SEAMLESS Co-Verification Seamless Co-Verification • Enables software & hardware development in parallel • Removes software from the critical path • Reduces the risk of hardware iterations • Provides accurate analysis of system performance • Increases overall product quality • Increases visibility into your hardware

7. System Profiler Performance Profile Database Balancing Performance & Detailwith Seamless HW Simulation Design Verification SW Execution Code Debug Coherent Memory Server

8. VHDL/Verilog/SystemC Pin Wrapper • Instruction Set Simulator (ISS) • Complete Instruction Set • Registers • Interrupt • Reset • Instruction Timing • Code Profiling • BUS Interface Model (BIM) • Peripherals • Bus Cycle Timing • Controllers (DMA, MMU, Cache …) • Memory/BUS tracing/profiling Seamless Processor Support Packages • High-performance ISS models core functionality • Integrated high-level debugger, e.g. XRAY, RealView and Multi • Interface to ModelSim and all popular Verilog and VHDL simulators Coherent Memory Server Memory Profiling

9. ARM7, ARM9 ARM10, ARM11, Cortex C6416, C64+, C55 Comprehensive CPU Support Oak, Teak, TeakLite, Palm 4K, 4KE, 5K, 20K, 24K PowerPC 603, 74x, 75x, 8xxx PowerQUICC I, II, III PowerPC 4xx Xtensa SC1200, SC1400 ZSP400, ZSP500 RM70xx, RM79xx Models also available for Analog Devices, ARC, ETRI, Faraday, Fujitsu, Infineon, Intel, Lucent, Matsushita, NEC, Philips, Renesas, Samsung, ST, Toshiba, Xilinx

10. ISS Seamless ISS Integrating the Software Domain with Assertion-based Verification

11. Profiler Views Software Profile Software Gantt Bus Load Bus Delay Memory Heat Map Power

12. Profiler: Views aligned to show cause & effect

13. High Level Models System High Level Model Executable Specification Software Hardware High Level Model Application BSP (drivers) • HDL - RTL • Design • Debug • Verification Co-Verification RTOS Software Hardware An Evolution of the “Traditional” Flow Paper Specification Virtual Prototype Consistent Verification Requirements follow-up

14. Transaction Level Modeling Algorithmic TLM RTL • This is a methodology, also known as TLM, that defines new abstraction levels above the register. • It is itself made of several stages, which gradually abstract from hardware implementation constraints but still with a structured view of the design. • Its goal is to reduce the number of events and the amount of data that has to be treated during simulation. • This modeling method is built as a set of interfaces that define how models communicates. A Generic CPU (B, C and ctrl) A Specific CPU - ISS (B, C and ctrl) TLM API TLM API TLM Channel Bus A C D TLM API TLM API D Mem B D Mem Transactions

15. The Performance of the Models A C D Function Call B A Generic CPU (B, C and ctrl) Transaction TLM Channel D Mem A Specific CPU - ISS (B, C and ctrl) Bus Clock D Mem

16. In Summary Functional Requirements Algorithmic Level Functional design and verification, exploration of the functional requirement list Explore the feasibility of requirements Uncommitted Systems System Exploration Level System executable specification, architecture exploration, HW/SW partitioning, mapping of functional list on HW/SW resources Partition HW and SW - Define the architecture Finalize the specification Hardware Transaction Level Hardware virtual prototyping, high level verification environment, architecture refinement, performance verification Create a first prototype of the HW Create a verification infrastructure “ESL Space” Hardware Committed Register Transfer Level Implement the hardware at register level Gates

17. Develop Algorithms using ANSI C++ No proprietary extension Focus on the functional intent Architectural Constraints Synthesize with Catapult C Explore the design space Find the optimal architecture Technology Files Untimed TLM Generate High Speed Models Verilog, VHDL, SystemC Accelerate system level verification Timed TLM Cycle TLM Generate Target Optimized RTL Faster and better than hand-coded For ASIC, FPGA or FPGA prototyping of ASICs Automatically Verify the RTL Generation of testbench infrastructure Seamlessly reuse original C++ test vectors Catapult C Synthesis – Algorithm to RTL

18. my Algorithm switch( m_state ) { case RES_WAIT : if( rsp_fifo._get( rsp ) ) { send_resp( rsp ); } break; PX for System Level CPU MEM Co-Proc MEM Bridge Peri 2 Peri 1 Perspecta • Modeling ‘components’ • Library builder and distributor • System Architecture • Assemble and modify design • Performance analysis • Throughput, bandwidth • Design validation • Functional and performance goals • HW/SW co-design • Full system integration • Verification • Hardware & software functional test Software Debugging Environment Perspecta Model Express Component Library System Analysis