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Entegra ’ s SDR Module

Entegra ’ s SDR Module. Dual 14 bit 65Msps A/D converters with a sampling bandwidth of 200MHz. Dual 14 bit 100Msps D/A converters. 2 million equivalent gate Xilinx V2000E FPGA On-board RAM: 1MB Sync Burst SRAM, 128kB dual-port SRAM.

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Entegra ’ s SDR Module

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  1. Entegra’s SDR Module • Dual 14 bit 65Msps A/D converters with a sampling bandwidth of 200MHz. • Dual 14 bit 100Msps D/A converters. • 2 million equivalent gate Xilinx V2000E FPGA • On-board RAM: 1MB Sync Burst SRAM, 128kB dual-port SRAM. • On-board high stability 10MHz reference and programmable DDS to support virtually any clock scheme currently in use. • 24/48 bit high speed LVDS or LV-TTL digital interface • 2MB FLASH ROM for FPGA configuration, also configurable via JTAG or DSP bus. • Omnibus DSP interface compatible with a range of Innovative Integration DSP cards. • Compact: 100mm x 160mm mezzanine mounting module.

  2. W-CDMA Downlink Simulator test-bed for experimenting with system partitioning in a user terminal

  3. Internal architecture of the physical channel processor FPGA

  4. The digital down-converter and filters

  5. Digital Up-Converter (DUC)

  6. Rake Receiver

  7. Searcher Receiver Matched Filter

  8. Eight Channel W-CDMA Transmitter

  9. Timing Controller

  10. DSP Software Structure

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