VEPIX53: Current status of the DUT

1. VEPIX53: Current status of the DUT Elia Conti 12/02/2014

2. Block diagram of the verification environment • top test lib • top base test • top test1,2… top env analysisenv hit env readoutenv trigger env top virtualsequencer PixelChipHarness Clock and resetgenerator PixelChip DUT hit_if analysis_if trig_if readout_if PixelChipInterfaces

3. DUT – Previous version PixelChipHarness Pixel Chip Pixel Region (PR) PR buffer Pixel matrix ToA HITS HIT PACKETS ToT ToT conv. Digital PUC TRIGGERLOGIC ..... ..... ..... TRIGGER TIME TAG END OF COLUMN (externalToAcounter) PIXEL BUSY FLAGS PR BUFFER FULL FLAG • PR buffer was not working as desired because each output was updated only when a nonzero packet was selected by trigger

4. PR buffer – New version Pixel RegionBuffer PR hit packets ToA + ToT from PUCs… ..... ..... ..... NB: matrix of registers (one per PUC) acksignals to PUCs ackReg matchReg deleteReg time tag(from trigger) Trigger matchinglogic • 3 registers in charge of sequential logic: • ackReg: generates ack signals to PUCs and enables write (push_front) to queue (independent from trigger matching) • matchReg: enables packet output from queue (pop_back) for 1 clock cycle • deleteReg: enables removal of non-triggered data from queue

5. Pixel Region– New version TOKEN_OUT Pixel Region Pixel matrix PR buffer ToA + ToT Derandomizing FIFO HITS TRIGGERLOGIC to columnbus ToT conv. Digital PUC ..... TRIGGER TIME TAG REQUEST TOKEN_IN • Derandomizing FIFO is a SV queue as well (infinite depth so far)

6. Pixel Chip –Column bus and columnarbiter Pixel Chip Column Bus TOKEN HITS Pixel Region TRIGGER End of Column ... TOKEN REQUEST_OR ExternalToACounter ColumnArbiter TOKEN_RETURN

7. Column Arbiter – Finite state machine token = 0 IDLE request_or= 1 token_return= 1 ACTIVE SERVE request_or= 1 AUTOMATICALLY token = 1 token = 0

8. Column Arbiter – Timing diagram example valid data packetlatency