William Stallings Computer Organization and Architecture 8th Edition

1. Chapter 5 Internal Memory William Stallings Computer Organization and Architecture8th Edition

2. Semiconductor Memory Types Memory Type Category Erasure Write Mechanism Volatility Random-access memory (RAM) Read-write memory Electrically, byte-level Electrically Volatile Read-only memory (ROM) Read-only memory Not possible Masks Nonvolatile Programmable ROM (PROM) Electrically Erasable PROM (EPROM) Read-mostly memory UV light, chip-level Electrically Erasable PROM (EEPROM) Electrically, byte-level Flash memory Electrically, block-level

3. Semiconductor Memory RAM Misnamed as all semiconductor memory is random access Read/Write Volatile Temporary storage Static or dynamic

4. Memory Cell Operation

5. Dynamic RAM Bits stored as charge in capacitors Charges leak Need refreshing even when powered Simpler construction Smaller per bit Less expensive Need refresh circuits Slower Main memory Essentially analogue Level of charge determines value

6. Dynamic RAM Structure

7. DRAM Operation Address line active when bit read or written Transistor switch closed (current flows) Write Voltage to bit line High for 1 low for 0 Then signal address line Transfers charge to capacitor Read Address line selected transistor turns on Charge from capacitor fed via bit line to sense amplifier Compares with reference value to determine 0 or 1 Capacitor charge must be restored

8. Static RAM Bits stored as on/off switches No charges to leak No refreshing needed when powered More complex construction Larger per bit More expensive Does not need refresh circuits Faster Cache Digital Uses flip-flops

9. Stating RAM Structure

10. Static RAM Operation Transistor arrangement gives stable logic state State 1 C1 high, C2 low T1 T4 off, T2 T3 on State 0 C2 high, C1 low T2 T3 off, T1 T4 on Address line transistors T5 T6 is switch Write – apply value to B & compliment to B Read – value is on line B

11. SRAM v DRAM Both volatile Power needed to preserve data Dynamic cell Simpler to build, smaller More dense Less expensive Needs refresh Larger memory units Static Faster Cache

12. Read Only Memory (ROM) Permanent storage Nonvolatile Microprogramming (see later) Library subroutines Systems programs (BIOS) Function tables

13. Types of ROM Written during manufacture Very expensive for small runs Programmable (once) PROM Needs special equipment to program Read “mostly” Erasable Programmable (EPROM) Erased by UV Electrically Erasable (EEPROM) Takes much longer to write than read Flash memory Erase whole memory electrically

14. Organization in detail A 16Mbit chip can be organized as 1M of 16 bit words A bit per chip system has 16 lots of 1Mbit chip with bit 1 of each word in chip 1 and so on A 16Mbit chip can be organised as a 2048 x 2048 x 4bit array Reduces number of address pins Multiplex row address and column address 11 pins to address (211=2048) Adding one more pin doubles range of values so x4 capacity

15. Refreshing Refresh circuit included on chip Disable chip Count through rows Read & Write back Takes time Slows down apparent performance

16. Typical 16 Mb DRAM (4M x 4)

17. Packaging

18. 256kByte Module Organisation

19. 1MByte Module Organisation

20. Interleaved Memory Collection of DRAM chips Grouped into memory bank Banks independently service read or write requests K banks can service k requests simultaneously

21. Memory errors Bit flips are a problem in memory and data communications Causes Marginal or failed component Noise Cosmic rays / alpha particles

22. Error Correction Hard Failure Permanent defect Soft Error Random, non-destructive No permanent damage to memory Detected using Hamming error correcting code

23. Error types Single-bit error Sent 00000010 Received 00001010 Start of Text (STX) Line Feed (LF) Multiple-bit errors Sent 01000010 Received 00001010 ASCII B Line Feed (LF) Burst errors (two or more consecutive bits) Sent 010000010100001001000011 Rec 010001100100001001000011

24. Error detection and correction Data message of m bits (gives 2m possible data messages) Add to this, rredundant bits that encode some kind of error detection and possibly correction Codeword sent of size n = m + r total bits The method of creating redundant r bits causes not all 2n codewords to be valid Receipt of an invalid codeword indicates an error

25. Hamming distance Defined as the number of bits by which codewords differ XOR two codewords together and count the number of 1's in the result 10001001 xor 10110001 00111000 Hamming distance of 3

26. Hamming distance continued If two codewords are ddistance apart, it takes d single-bit errors to change one into the other All 2m messages are possible, and it is possible to create a list of all legal 2n codewords From this list, find the two legal codewords whose Hamming distance is the smallest This gives the Hamming distance for the entire code

27. Hamming distance continued To detect d errors, we need a code of at least d + 1 Hamming distance To correct d errors, need a code of at least 2d + 1 Hamming distance

28. Parity bit for redundancy Append a single bit Even or odd parity chosen in advance In odd parity, if the count of ones in the message m is an even number we add a 1 parity bit to make the count odd m = 1011010 (4 ones) parity bit = 1 codeword = 10110101 (5 ones) Odd parity example

29. Parity bit continued A single parity bit gives a code with a Hamming distance of 2 Single parity bit can detect a single bit error, nothing more

30. Error correction Need a code with a larger Hamming distance than a single parity bit Suppose a code with these valid codewords: 0000000000 0000011111 1111100000 1111111111 What is the Hamming distance of the code?

31. Error correction continued Clearly this code has a Hamming distance of 5 5 = 2d + 1, 2d = 4, d = 2 This code can correct double-bit errors What if we receive 0000000111? From the valid codewords, we would select 00000111111 A triple-bit error would not be corrected properly

32. Hamming error correction in practice Design a code with single-bit error correction Messages of size m divided into blocks with r redundancy bits per block Need a Hamming distance of at least 3 The number of r bits needed depends on size m Hamming devised such a code in 1950 that minimizes r Bits 1, 2, 4, 8, 16, etc are check bits (r redundant) All remaining bits are message bits (m message)

33. Hamming code Redundant bits store parity for some group of message bits For each message bit - Break down position number shown as power of 2 sum Upon message receipt - Check each redundant bit's group for parity If check fails, add number of its parity bit to a counter Success is counter = = 0, failure contains position of bit failure

34. Hamming code continued position k checked by sum of powers of 2 parity k 20 21 22 23 1 = 1 2 = 0 + 2 3 = 1 + 2 4 = 0 + 0 + 4 5 = 1 + 0 + 4 6 = 0 + 2 + 4 7 = 1 + 2 + 4 8 = 0 + 0 + 0 + 8 9 = 1 + 0 + 0 + 8 10 = 0 + 2 + 0 + 8 11 = 1 + 2 + 0 + 8 12 = 0 + 0 + 4 + 8

35. Hamming code continued Odd bits have parity at bit 1 Bits 2-3, 6-7, 10-11, 14-15, 18-19, ... have parity at bit 2 Bits 4-7, 12-15, 20-23, ... have parity at bit 4 Bits 8-15, 24-31, 40-47, ... have parity at bit 8 and so on Position 1: Check a bit, skip a bit, check a bit, skip a bit Position 2: Check 2 bits, skip 2 bits, ....

36. Hamming example Choose ASCII 'A' = 01000001 (6510 or 0x41) Powers of 2 positions are parity (even) ___ ___ 0 ___ 1 0 0 ___ 0 0 0 1 k = 12 3 4 5 6 7 8 9 10 11 12 Bits 1, 3, 5, 7, 9, 11 = __ 01000 = Odd number of ones, what is bit 1? Bits 2-3, 6-7, 10-11 = __ 00000 = Even number of ones, what is bit 2? Bits 4-7, 12-15 = __ 100 1 = Even number of ones, what is bit 4? Bits 8-15 = __ 0001 = Odd number of ones, what is bit 8?

37. Types of Hamming codes ASCII is really a 7-bit code 7 data bits in an 11-bit codeword 'H' 1001000 encoded as 00110010000 Not very efficient for memory 72/64 frequently used 64 data bits, 8 check bits Allows Single Error Correction, Double Error Detection (SEC-DED)

38. Single error correction example Suppose we have 12-bit Hamming code Memory value read is 0XE4F Is this valid? If not, what is wrong?

39. Error Correcting Code Function

40. Advanced DRAM Organization Basic DRAM same since first RAM chips Enhanced DRAM Contains small SRAM as well SRAM holds last line read (c.f. Cache!) Cache DRAM Larger SRAM component Use as cache or serial buffer

41. Synchronous DRAM (SDRAM) Access is synchronized with an external clock Address is presented to RAM RAM finds data (CPU waits in conventional DRAM) Since SDRAM moves data in time with system clock, CPU knows when data will be ready CPU does not have to wait, it can do something else Burst mode allows SDRAM to set up stream of data and fire it out in block DDR-SDRAM sends data twice per clock cycle (leading & trailing edge)

42. SDRAM

43. SDRAM Read Timing

44. RAMBUS Adopted by Intel for Pentium & Itanium Main competitor to SDRAM Vertical package – all pins on one side Data exchange over 28 wires < cm long Bus addresses up to 320 RDRAM chips at 1.6Gbps Asynchronous block protocol 480ns access time Then 1.6 Gbps

45. RAMBUS Diagram

46. DDR SDRAM SDRAM can only send data once per clock Double-data-rate SDRAM can send data twice per clock cycle Rising edge and falling edge

47. DDR SDRAM Read Timing

48. Simplified DRAM Read Timing

49. Cache DRAM Mitsubishi Integrates small SRAM cache (16 kb) onto generic DRAM chip Used as true cache 64-bit lines Effective for ordinary random access To support serial access of block of data E.g. refresh bit-mapped screen CDRAM can prefetch data from DRAM into SRAM buffer Subsequent accesses solely to SRAM

50. Reading The RAM Guide RDRAM