MAC Processor for BASUMA Wireless Body Area Network

1. Z. Stamenković, D. Dietterle, G. Panić, W. Bocer, G. Schoof, and J.-P. Ebert MAC Processor for BASUMA Wireless Body Area Network

2. Motivation • Up to date no stable operating BAN available • Enable exchange between sensors for intelligent reasoning about patients state • Data rates > 1 Mbps at low power are challenging • Essential for small battery-powered devicesHurry-up-and-sleep approach • Smart wireless medical sensors • Enable continuous health monitoring • Single chip solution (SOC) • Lowers power consumption, weight, and allows different packaging

3. Body Area System for Medical Applications … … … … Heart transplantation Heart transplantation Heart transplantation Heart transplantation l Breast cancer Breast cancer Breast cancer Breast cancer Apps COPD COPD COPD COPD Lung Lung ECG ECG SpO2 SpO2 ROS ROS Mobile Mobile … … Sound Sound Sensor Sensor Sensor Sensor Sensor Sensor Phone Phone Monitor Monitor Middleware Middleware SW SW Application Framework BASUMA Application Framework Wireless Communication Protocols Wireless Communication Protocols IEEE 802.15.3 IEEE 802.15.3 Embedded Operating System Embedded Operating System Reflex OS Reflex OS Processor Processor Radio Radio HW HW LEON2 LEON2 Ultra Wideband (UWB) Ultra Wideband (UWB)

4. BASUMA • Body Area System for Ubiquitous Multimedia Applications • Generic wireless communication platform • Long-term health monitoring of chronically ill patients

5. BASUMA Communication Module

6. IEEE 802.15.3 MAC Protocol • IEEE 802.15.3 standard provides • Ad-hoc networking • Quality of service and security • Various power management modes • Physical layer data rates from 11 to 55 Mbit/s • Medium Access Control (MAC) protocol functionality • Data path • Cyclic redundancy check (CRC) sum calculation • Encryption and decryption of the frame payload • Interfacing with the physical layer and frame buffering • Control path • Profiling of the software using LEON-2 instruction set simulator • Time-critical protocol functions are iteratively removed from the software model and put into a hardware component

7. MAC Protocol Model

8. Protocol Functions Designed in Hardware • In receive direction, to retrieve frame data from the physical layer byte by byte, perform filtering and CRC check, and to store the data by means of direct memory access • In transmit direction, to retrieve frame data from a memory location, calculate and append the check sum, and to push the data to the physical layer • To signal a successful reception or transmission of a frame to the processor by an interrupt • To analyze received and transmitted beacon frames and extract information on channel time allocations • To manage a queue of frames and to select an appropriate frame for transmission • At the start of a time slot or following a frame transmission, to query a new frame from the queue and, in the case that the frame must be acknowledged, wait for the acknowledgment frame • To perform the backoff procedure in the contention access period • To send an acknowledgment at the right time upon reception of a frame that needs to be acknowledged • To calculate the actual duration of a frame transmission based on its payload length and data rate

9. Architecture of MAC Protocol Accelerator

10. Flash Interface

11. System Architecture BIST BIST UART 0 UART 0 BASUMA BASUMA DSU+ DSU+ 8 kByte 4 kByte MAC MAC UART UART UART 1 UART 1 I I - - Cache Cache LEON LEON - - 2 2 16 x GPIO Bridge AHB AHB 16 x GPIO Bridge Core Core APB APB 8 Reg. Windows 8 Reg. Windows Memory Memory AHB AHB IRQ IRQ 2 x 2 x CTL CTL CTL CTL 4 kByte 8 kByte CTL CTL Timer Timer D D - - Cache Cache 64 kByte 64 kByte Scan Test Scan Test BIST BIST FLASH FLASH SRAM SRAM FLASH FLASH

12. Applications Applications System System Specification Specification Library Database Library Database New Modules Predefined Modules Configurable Modules New Modules Predefined Modules (RTL, standard cells, Customisable Modules ( synthesised net-list, SDF ( synthesisable RTL code) synthesised net-lists, layouts) ( synthesisable RTL code) and/or LEF) HDL Top Module Definition HDL Model Definition no no Simulation OK? Simulation OK? Logic Re-synthesis yes yes Sufficient? Logic Synthesis Logic Synthesis no no Simulation OK? Simulation OK? Test Benches Test Benches Layout Re-synthesis yes yes Sufficient? Layout Generation Layout Synthesis no Simulation OK? Simulation OK? yes Final Chip Layout Design Flow

13. Implementation • Installation of the LEON-2 release • Adaptation of the configuration tool (to include IHP’s library) • VHDL coding of MAC protocol accelerator and flash interface • Implementation of data and instruction caches including BIST • Logic synthesis of the design • Implementation of scan chain • Generation and verification of the chip layout • Simulation (functional, post-synthesis and post-layout net-list) • Scan test vectors generation (ATPG) • BIST and scan test simulation • Adaptation of testbenches (SPARC CC installed) • EVCD test vectors generation (with and without timing data) • Test specification

14. Chip Features

15. Summary • Hardware/software co-design and implementation of the processor configured to support IEEE 802.15.3 MAC protocol of the Body Area System for Ubiquitous Multimedia Applications (BASUMA) • Implemented SOC is a good candidate for the MAC processor of the BASUMA communication module in respect of performance, speed, and power • Next phase in development of the wireless body area network technology at IHP • TANDEM project