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CS147

CS147 . Lecture 9. Sequential Circuits and Finite State Machines Prof. Sin-Min Lee Department of Computer Science. Example of combinational and sequential logic. Combinational: input A, B wait for clock edge observe C wait for another clock edge observe C again: will stay the same

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CS147

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  1. CS147 Lecture 9 Sequential Circuits and Finite State Machines Prof. Sin-Min Lee Department of Computer Science

  2. Example of combinational and sequential logic • Combinational: • input A, B • wait for clock edge • observe C • wait for another clock edge • observe C again: will stay the same • Sequential: • input A, B • wait for clock edge • observe C • wait for another clock edge • observe C again: may be different A C B Clock

  3. Basically • Combinational: • No internal state (or memory or history or whatever you want to call it) • Output depends only on input • Sequential: • Output depends on internal state • Probably not going to be on this midterm since formal lecture on it started last Thursday.

  4. Design hierarchy system control data-path coderegisters stateregisters combinationallogic multiplexer comparator register logic switchingnetworks

  5. J Q CLK To Be Designed D Q’ K Recap - Sequential Systems • Example: • Design a D FF with a JK FF and AND, OR, NOT gates:

  6. 0 1 Sequential Systems - Cont. D(t) 0- 1--1 -0JK

  7. D - - 1 0 0 1 - - Q K = D’ J = D D • D J Q CLK Q Q’ K Sequential Systems - Cont.

  8. Analysis of Sequential Systems • Goal: • Decide the timing and functional behavior from the implementation of a sequential system composed of FFs and logic gates • Types: • Functional analysis • Timing analysis

  9. Characteristic Equation of FFs

  10. State Transition: Output: Example

  11. Input Output State Encoding Scheme State Transition Table

  12. Example (Cont’d) High-Level Specification

  13. State Diagram Time-behavior Specification

  14. Example

  15. JAKA, JBKB 10,01 01,01 10,10 01,10 00,00 01,00 10,10 11,10

  16. Example 8.7 (Cont’d)

  17. Example Design a single-input, single-output synchronous sequence detector with input labeled by x. Every time a pattern of sequence 0101 is detected, this sequence detector produces an output y = 1. Otherwise, y = 0. For example, when the input sequence is 01010100, the corresponding output sequence is 00010100. Step 1: Derive the state digram. We can construct the state diagram of the detector with four states, A, B, C, and D. Why four? What do they mean? A: ground zero; we don’t have any of the desired sequence. B: just got the leading 0 C: just got 01 D: just got 010 If we’re in state D and we see ‘1’ on x, we set the output y high.

  18. Step 2: Derive the state table. Step 3: It is impossible to reduce the number of states for this example. If A and B are equivalent, A and C must be equivalent, which implies B and D are equivalent. The latter (B and D are equivalent) is not true, and hence A and B are NOT equivalent. We may apply the argument above to all pairs of states to find out that no two states are equivalent.

  19. Step 4: Assign binary values to each state. Since we have four states, we need two state variables, S1 and S0, and the values assigned to the four states are         ,          ,         , and          . Now the state table looks like:

  20. Step 5: From Step 4, we know that we need two flip flops because we have two state variables. We will discuss two cases: (1) use of D flip flops; (2) use of JK flip flops to implement the sequence detector. Step 6: Derive the circuit excitation and output tables. If we use the D flip flops, then we have

  21. On the other hand, if we use the JK flip flops, we have

  22. During the design phase, we usually know the transition from present state to next state and need to find the FF input condition that will cause the required transition. That is, we need to know how to exercise the circuit so that given the present state, the circuit will go to some specific next state. Take J-K flip flops as examples. Given the present state 0, to drive the circuit so that its next state is 0, we may either keep the circuit unchanged (i.e., applying J=K=0) or reset the circuit (i.e., applying J=0, K=1). That is, the inputs to the FF are J=0 and K= don't care. Similarly, given the present state 0, to drive the circuit so that its next state is 1, we may either set the circuit (i.e., applying J=1, K=0) or toggle the circuit (i.e., applying J=K=1). That is, the inputs to the FF are J=1 and K = don't care.

  23. Step 7: Derive the circuit output functions and the flip-flop input functions. If we use D flip flops, we should derive, using K-maps, D1 and D0 as functions of the present states S1, S0, and the input x, respectively. On the other hand, if we use JK flip flops, we should derive J1, K1, J0, and K0 as functions of the present states S1, S0, and the input x. For example, to derive the expression for J1, we construct the following K-map: Hence, J1= S0x.

  24. To derive the expression for K1, we construct the following K-map: Hence,

  25. Registers and Counters • A n-bit register is a set of n flip-flops that is capable of storing n bits of binary information. With added combinational gates, the register can perform data-processing tasks. • A counter is a register that goes through a predetermined sequence of states upon the application of clock pulses.

  26. Example Counter design: Use J-K flip flops to design a counter that repeatedly counts the following binary sequence: 0, 1, 2, 4, 5, and 6. Steps 2 through 6: Derive the state table and the circuit excitation table

  27. Note that two states, 011 and 111, are not included in the count, and hence their corresponding J and K inputs are don't care. Step 7: Derive the circuit output functions. By use of K-maps (with those don't cares figured in), the simplified functions are

  28. The logic diagram of the counter is shown below.

  29. Consider a sequential circuit shown in the following Figure. It has one input x, one output Z and two state variables Q1Q2 (thus having four possible present states 00, 01, 10, 11).

  30. The behaviour of the circuit is determined by the following Boolean expressions: Z = x*Q1 D1 = x' + Q1 D2 = x*Q2' + x'*Q1' These equations can be used to form the state table.

  31. Z = x*Q1 D1 = x' + Q1 D2 = x*Q2' + x'*Q1' These equations can be used to form the state table.

  32. The state diagram for the sequential circuit in Figure 4 is shown in Figure 5.

  33. Excitation tables • The design process for an FSM involves determining the combinatorial logic to be used as input to each flip-flop input line. The SR and JK flip-flops have two lines, and it is possible that there may be more than one possible combination of inputs which will cause a flip-flop in state X to go to state Y. We therefore need to construct what are known as excitation tables. These define the input combinations to a flip-flop to implement defined changes of state.

  34. Implementation using SR-type Flip-Flops

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