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Lecture 16:Exception Processing

Lecture 16:Exception Processing. Computer Engineering 211 Spring 2002. ISP address 4 byte. Vector#. 1 2 3 4 5 6 C. System reset Data addr error Inst addr error Ext. interrupt Alignment error System call. Vectored Interrupts:Motorola.

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Lecture 16:Exception Processing

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  1. Lecture 16:Exception Processing Computer Engineering 211 Spring 2002

  2. ISP address 4 byte Vector# 1 2 3 4 5 6 C System reset Data addr error Inst addr error Ext. interrupt Alignment error System call Vectored Interrupts:Motorola Each exception & interrupt has a 8-bit vector #: 0-255 (for Motorola 68xxx family) Starting address of ISP = vector#*4 + starting address of vector table = 0x1000 + 3*4 (for data addr error).

  3. Addr: 0x00000000 Vector 0 Vector 1 Addr: 0x00000100 Vector 2 Addr: 0x00000200 Vector 31 Addr: 0x00001f00 Vectored Interrupts:PPC PPC maintains an exception vector table. Only 32 vectors available. Each vector is given 100 words of space in exception vector table. A primitive ISP goes in that space.

  4. Exception processing: prioritization If multiple exceptions/interrupts raised simultaneously, how do we prioritize them? In general: internal exceptions (software raised) are always given higher priority than the external interrupts (hardware device initiated). Within software exceptions, there might be multiple levels of prioritization: 2 in MIPS. Within external interrupts, multiple levels of priority: 6 in MIPS.

  5. Cause Register 4 Pending interrupts IP5 IP4 IP3 IP2 IP1 IP0 SW1 SW0 00 Cause code 00 Exception processing: prioritizationcontd. Look at all the pending interrupts at the entry into the exception-handler. If more than one is 1, choose based on the priority. Can a higher priority interrupt pre-empt the ISP for a lower priority interrupt? There can be nested exception service procedures!

  6. Exception processing: Control transfer • Exception-handler is just like any other procedure. • Calling is not done through a procedure call. • It is called by the processor controller by forcing • its address 0x80000080 into PC. What should be saved before forcing 0x80000080 into PC (so that we can resume the interrupted program)? Current program’s state including its address.

  7. K/U I.E. 8 15 Interrupt mask Exception processing: Control transfer Contd. Right before PC  0x80000080, the current PC is saved in EPC: PC  EPC (Exception PC). EPC is Reg. 14 in co-processor 0: mfc0 $t0, $14 or mfc0 $t0, $EPC Other program state is kept in Status Register:

  8. Exception processing: Control transfer Contd. While in exception-handler, can another exception be accepted? EPC gets overwritten similar to $ra! One of the first acts in exception-handler should be to save EPC, cause, and status register on a stack. While saving these registers, should we disable all the interrupts?

  9. At entry into exception-handler: 0 0 old prev. current K/U K/U K/U K/U K/U K/U K/U I.E. I.E. I.E. I.E. I.E. I.E. I.E. 0 0 Exception processing: Control transfer Contd. • All exceptions are disabled. • K/U=0: kernel mode (supervisor mode).

  10. Exception processing: Control transfer Contd. exception-handler: mfc0 $k0, $cause mfc0 $k1, $EPC sw $k0, -4($sp) sw $k1, -8($sp) addi $sp, $sp, -8 mfc0 $t0, $status ori $t0, $t0, 0x1 mtc0 $status, $t0 andi $k0, $k0, 0x3c beq $k0, $zero, interrupt --- --- exception-handler() { /* keep the interrupts disabled */ (1) save EPC, cause, status regs on system stack. (2) enable interrupts. (3) decode cause and call appropriate ISP. }

  11. RI=1: recoverable Machine State Register (MSR) 0 EE PR 0 IP IR DR 0 0 RI LE IP=0: exception Vector table Starts at 0x000 else 0xfff PR=0: supervisor =1: user EE=ext. interrupt enable =0: disable =1:enable LE=0 Big-endian Exception processing: Control transfer PPC

  12. Machine Status Save/Restore Register 0 (SRR0) PC saved here Machine Status Save/Restore Register 1 (SRR1) Exception specific info Save MSR bits 0000 000000 1-4 10-15 E E P R I P R I L E MSR PPC Exception Registers

  13. On an exception: IL E E E P R I P R I L E 0 0 0 MSR PPC Exception Registers mtspr SRR0, r2: r2  SRR0 mfspr r3, SRR1: SRR1  r3 mtmsr r2: r2  MSR mfmsr r3: MSR  r3 Each exception handler must save SRR0, SRR1, and MSR before enabling exceptions (EE=1).

  14. PPC Exception Priorities Non-maskable, asynchronous: Priority 1: System reset Priority 2: Machine check Synchronous, maskable: instruction dependent ones such as alignment, FP: Priority 3, 4. Asynchronous, maskable: external interrupt (priority 5) decrementer (priority 6).

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